00:18 <_whitenotifier-d> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JEQb6

00:18 <_whitenotifier-d> [YoWASP/nextpnr] whitequark 627ed3a - Update dependencies.

00:58 <_whitenotifier-d> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JEQh5

00:58 <_whitenotifier-d> [YoWASP/yosys] whitequark 93df8d6 - Update dependencies.

02:26 <_whitenotifier-d> [nmigen] modwizcode commented on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JE7Ot

12:43 <d1b2> <286Tech> I'm trying to instantiate a Verilog module and it works fine, but I was wondering if it's possible to assign a 1 bit value to a parameter. The resulting Verilog code always has a 32-bit value assigned to the parameter even if I instantiate it with p_PARAM_NAME=0b1 for example.

13:04 <mwk> p_PARAM_NAME=Const(<value>, <width in bits>)

13:04 <mwk> 0b1 is transformed into 1 by the time the Python parser is done with it, nMigen has no way of seeing the original token

13:28 <d1b2> <286Tech> Ah cool, thanks!