<_whitenotifier-d>
[nmigen] alanvgreen commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JETSD
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<lkcl>
tpw_rules, ktemkin: dropped back in again, nmigen-instance was again the last topic discussed. seems v. popular :)
<lkcl>
alanvgreen, awygle, whitequark: i've already written and designed a stream abstraction library. it took about 5-6 months to specify, design, and write. all source code and unit tests is here https://git.libre-soc.org/?p=nmutil.git;a=tree;f=src/nmutil
<lkcl>
there are over 40 different examples of ways to use it.
<lkcl>
also there are single pipe and multi pipe (fan-in, fan-out) examples, all of which are in use, and all of which have gone into silicon in July.
<lkcl>
it also implements (and demonstrates) the multiple different *types* of ready/valid usage. some people require full pipelined ready/valid whilst others prefer "global stall". all of these options are possible (and demonstrated with unit tests)
<lkcl>
it turns out that FIFOs are a form of ready/valid streaming
<lkcl>
to the point where i took the chisel.io "queue" library - used a lot in the chisel3 version of the ready/valid stream system - and put a nmigen FIFO class API on it
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<lkcl>
then created an example with it.
<lkcl>
so i can confirm, yes, FIFOs are pretty much synonymous with pipeline stages
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<lkcl>
one abstraction that was considered critically important (enough to spend a deep chunk of the 5-6 months development time that went into nmutil) was abstraction of the combinatorial "stages"
<lkcl>
pipeline stages *MAY* be Mealy FSMs but it's recommended that they be Moore FSMs (pure combinatorial)
<lkcl>
the Stage API abstraction then allows CHAINING of multiple such combinatorial blocks together
<lkcl>
where each "stage" has a means and method of specifying both its input and its output format
<lkcl>
and the Stage API can then *AUTOMATICALLY* and inherently know how to chain "Stages" together
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<lkcl>
the result of chaining combinatorial "Stages" together... presents.... an object with the exact same Stage API, but simply presenting the "input" record of its first stage and the "output" stage of its last.
<lkcl>
then ControlBase is quite similar to that, but allows sync get involved
<lkcl>
which maps to a chisel3.io-ported Queue class btw (and was what we made conform to the standard nmigen FIFO)
<lkcl>
the options for chisel3.io queue library allow "first-word fall-thru" as well as "pipeline mode"
<lkcl>
these FUNDAMENTALLY change the interaction and the rules of engagement between the ready/valid signalling
<lkcl>
oh - one other feature that i experimented with: using the exact same API to create Finite State Machines instead of pipelines
<lkcl>
this was VERY tricky, but doable
<lkcl>
it came down to the fact that when the Stages are split out into combinatorial blocks, it's possible to interact with them and use them for purposes _other_ than just "pipelines"
<lkcl>
i did successfully create hybrid code for an IEEE754 unit that could be EITHER a pipeline OR a FSM (similar to jon dawson's IEEE754 FPU)
<lkcl>
in order to significantly save on gates (important for embedded FPGA)
<lkcl>
i sincerely apologise to everyone here, i have been so busy i hadn't even noticed that there was a discussion and plans to duplicate the functionality that's been in production use for nearly two years, now
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<d1b2>
<Max> Little Question: Say I want to have a List of Signals I want to address using another signal. How can I do that in nmigen? If I put the Signal in a Python List, I get KeyErrors.
<tpw_rules>
an Array
<tpw_rules>
is what you need
<d1b2>
<Max> That was fast! Thanks! 🙂
<alanvgreen>
lkcl: woah, that's a lot. Am working my way through it
<alanvgreen>
I quite like the names "next" and "prev" instead of "source" and "sink".
<lkcl>
alanvgreen: it was 5+ full-time months, two of us spent i think it was 2-3 months doing nothing but write back and forth discussing the design
<lkcl>
i mean, we *had* to get it done, and get it done pretty fast, because we were - are - critically relying it for the Libre-SOC core
<lkcl>
the names "next" and "prev" were also deliberately chosen because they're both 4 letters long
<lkcl>
that means that, vertically, they line up [and autopep8 doesn't mess up the vertical alignment]
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<anuejn>
alanvgreen: I also want to throw upstream and downstream into the name-bikeshedding bowl ;)
<agg>
Producer and consumer are also equal length nouns :p
<agg>
But "next" is a python built-in so maybe not ideal for use as a common variable name?
<anuejn>
agreed
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