02:43 <whitequark> or that, perhaps

14:08 <_whitenotifier-d> [nmigen] andresdemski commented on issue #603: RTLIL sync rules are Verilog-specific and should not be emitted - https://git.io/J05vb

14:17 <lkcl> "<ktemkin> since this gets asked a lot, just wrote up a quick post we can link: https://lab.ktemkin.com/post/nmigen-instance/"

14:17 <lkcl> nice

14:18 <lkcl> perhaps it would be good to add as an example to the main nmigen examples?

14:21 <lkcl> hmmm there is one

14:21 <lkcl> https://github.com/nmigen/nmigen/blob/master/examples/basic/inst.py

14:22 <lkcl> but hmm without the corresponding verilog source (and excellent explanation you provide) it's not obvious what's going on

14:53 <ktemkin> the example could probably use some commenting explaining how and why things work, but probably that effort is better spent working on the docs, at some point

16:06 <xxov> hey, is it possible to 'include' a verilog module in an nmigen project or have an nmigen module produce custom a verilog string?

16:06 <tpw_rules> xxov: https://lab.ktemkin.com/post/nmigen-instance/

16:07 <tpw_rules> and also https://github.com/tpwrules/tasha_and_friends/blob/6948866e7c064a0766fb899a48d2dbcbc392ac73/tasha/gateware/c5g/generate.py#L117

16:07 <xxov> tpw_rules: thanks! google doesn't seem to knwo about this page

16:07 <tpw_rules> it's very new

17:21 <lkcl> ktemkin: true

17:22 <lkcl> xxov, lol ktemkin just wrote that example because of the number of times people ask :)

17:22 <lkcl> which is a great sign, if you think about it.

17:22 <lkcl> it means that lots of people are looking to integrate nmigen into existing projects. kinda cool

17:23 <lkcl> i wish i had more time to help improve nmigen itself.

17:23 <lkcl> best i can do is help find NLnet funding for people who do want to do that.

17:24 <lkcl> NLnet's latest "Assure" theme is no longer restricted to EU / EEC residents