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<lsneff>
Sorry, which part is cxxsim and which is cxxrtl?
<whitequark>
cxxrtl is the C++ thing in Yosys
<whitequark>
cxxsim is the Python thing in nMigen (that uses cxxrtl)
<lsneff>
Ah, I gotcha
<lsneff>
Thanks
<lsneff>
If I'm going to support vcd in ligeia, I need to deal with z (high impedance) and x (unknown), correct?
<lsneff>
I'm thinking of maybe only having bit arrays, and the display layer can interpret them in terms of binary, quaternary, utf-8, whatever
<whitequark>
z and x are often necessary, yes
<whitequark>
especially x
<whitequark>
how else do you represent uninitialized values?
<lsneff>
That's a reasonable point
<lsneff>
Should everything be four-valued logic?
<whitequark>
would say both representations are useful
<lsneff>
Alright
<d1b2>
<DX-MON> at minimum - VHDL and Verilog both technically have support for l, L, h and H too indicating various kinds of weekly driven signals (think this might be used in ASIC flows to indicate the need for things like Open-Collector drivers, as opposed to totem-pole)
<d1b2>
<DX-MON> if you're trying to build a general-purpose replacement for VCD, then I would strongly suggest this would be necessary
<mwk>
verilog is... fun
<lsneff>
What do you think, whitequark, should svcb be that general?
<lsneff>
given my admitably limited experience with verilog, fun is not how I'd describe it
<DX-MON>
reasonably sure mwk was being sarchastic
<mwk>
technically you have only 4-valued logic, but you can have drivers driving them with 7 different strengths
<lsneff>
okay
<mwk>
so you don't exactly have strong/weak values like vhdl does, but it does have strength as a separate thing
<mwk>
and they combine in quite complex ways, particularly when pass transistors with x signals on gates are involved
<mwk>
(you can have a net that has a value of "1, strong", "1, weak", or "1, but strength is unknown somewhere between week and strong", "x, and strength is between weak 0 and strong 1", ...)
<lsneff>
And high impedance
<lsneff>
I see
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<cr1901>
>and they combine in quite complex ways, particularly when pass transistors with x signals on gates are involved
<cr1901>
Where in the spec can I learn more about this? I know of strength, but not the "truth tables"