whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
<_whitenotifier-a> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JReuY
<_whitenotifier-a> [YoWASP/nextpnr] whitequark 0000a84 - Update dependencies.
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<_whitenotifier-a> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JRerY
<_whitenotifier-a> [YoWASP/yosys] whitequark a725f91 - Update dependencies.
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<tpw_rules> whitequark: does anything internal to nmigen or yosys use the name "\initial " for a register in verilog? for some reason things i build are duplicating that name. and if i remove the name initial from my code, that name does not disappear from the verilog. i haven't dug very deep yet but does this jog your memory?
<mwk> hm, verilog backend I think?
<mwk> as in, Verilog output module in yosys
<mwk> yeah, that'd be it
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<vup> mwk: tpw_rules: I think this is the problem: https://github.com/YosysHQ/yosys/issues/2914
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<tpw_rules> vup: thank you for figuring that out
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