<_whitenotifier-a>
[nmigen] lethalbit opened pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRGdd
<_whitenotifier-a>
[nmigen] codecov[bot] commented on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRGby
<_whitenotifier-a>
[nmigen] codecov[bot] edited a comment on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRGby
<_whitenotifier-a>
[nmigen] codecov[bot] edited a comment on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRGby
<_whitenotifier-a>
[nmigen] codecov[bot] edited a comment on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRGby
emeb_mac has quit [Ping timeout: 258 seconds]
<_whitenotifier-a>
[nmigen] whitequark commented on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRGNd
emeb_mac has joined #nmigen
<_whitenotifier-a>
[nmigen] lethalbit commented on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRGAr
nak_ has joined #nmigen
nak has quit [Ping timeout: 258 seconds]
emeb_mac has quit [Quit: Leaving.]
peeps[zen] has joined #nmigen
sm2n_ has joined #nmigen
peepsalot has quit [Ping timeout: 256 seconds]
sm2n has quit [Ping timeout: 256 seconds]
someone-else has joined #nmigen
Niklas[m]1 has joined #nmigen
<_whitenotifier-a>
[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15 and XC7A35 and their common daughterboard - https://git.io/JGvXe
<_whitenotifier-a>
[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15 and XC7A35 and their common daughterboard - https://git.io/JGvXe
<_whitenotifier-a>
[nmigen-boards] hansfbaier synchronize pull request #154: Add support for QMTech Boards EP4CE15 and XC7A35 and their common daughterboard - https://git.io/JGvXe
someone-else has quit [Quit: Connection closed]
<_whitenotifier-a>
[nmigen] anuejn commented on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRnRS
someone-else has joined #nmigen
urja has quit [Ping timeout: 240 seconds]
urja has joined #nmigen
samlittlewood has quit [Ping timeout: 272 seconds]
samlittlewood has joined #nmigen
emeb has joined #nmigen
GenTooMan has quit [Ping timeout: 258 seconds]
GenTooMan has joined #nmigen
<_whitenotifier-a>
[nmigen] mithro commented on pull request #624: sim: Implemented signal notability for use in generating actually useful GTKW files - https://git.io/JRcXa
emeb has quit [Quit: Leaving.]
emeb_mac has joined #nmigen
mcfrdy has quit [Quit: quit]
mcfrdy has joined #nmigen
mcfrdy has quit [Quit: quit]
mcfrdy has joined #nmigen
<Degi>
How do I debug something like "ERROR: Conflicting init values for signal 1'0 ($flatten\phy.\phy.\U$$5.$signal$4 [8] = 1'0 != 1'x)."
<Sarayan>
Do you have something called phy in your stuff?
<Degi>
Yes, two things
<Degi>
But the phy object has a lot of submodules
<Degi>
Oh, can I get a more verbose error by giving the modules a verbose name in m.submodules? Like m.submodules.xyz = abc instead of m.submodules += abc
<Sarayan>
possibly, yes, sounds like a good idea
<mwk>
Degi: if this is a pure-nmigen design, it has a good chance of being a yosys bug; could I see the RTLIL?
<Degi>
uhh, sure... It might be a bit big, is it build/top.il?
<mwk>
yes, that should be it
<Sarayan>
true, x is not supposed to exist in pure nmigen isn't it?
<mwk>
yes, plus if nmigen blows up with non-obvious yosys error, it's either a yosys bug or nmigen bug
<Degi>
Oh, should I update yosys first maybe
<mwk>
okay
<mwk>
so this *is* a yosys bug
<mwk>
a fascinating interaction of at least 5 different things that have to go wrong
<mwk>
1) nMigen brings out unnamed submodule's port to parent module as submod_name$signal$123 (a public name) while it's $signal$123 (a private name) in the actual module
<mwk>
2) flatten throws both of them into one namespace; it mangles the name but doesn't change private/public type
<mwk>
3) opt_clean considers the parent module's public name more important than actual module's private name, and thus considers it canonical, reconnecting the DFF output from module's signal to parent's signal, but NOT moving the init attribute (arguably bug)
<mwk>
4) opt_merge notices two FFs with the above arrangement have identical identical inputs and settings, and can thus be merged; however, it fails to remove init value bit because it's not on the same wire as FF's Q output anymore, and it stays there (bug here)
<mwk>
[there are two different aliased wire bits having an init value at this point]
<mwk>
5) opt_dff notices, for unrelated reason, that this FF's value can never actually change and converts it to a const driver, removing the init value bit in the process, but only notices *one* of the two (arguably bug here)
<mwk>
and then whatever pass next constructs a FfInitVals helper blows up because there is now somehow an init value bit on a constant
<mwk>
now, this is very definitely a yosys bug, but given RTLIL being quite underdefined in general, I cannot quite tell *which* parts of this are truly buggy, and which just happen to take advantage of RTLIL's sloppiness
<mwk>
also, I don't think this can even be reproduced with Verilog input, since that'd involve somehow making a FF with unnamed output
<mwk>
whitequark: this mess is of course not an nMigen bug, but is the "private signal appears in parent under public name" thing intended?
<mwk>
... oh and also the optimized part of the dff needs to only attach to part of a wire, or the bug doesn't happen for unrelated reasons
<Degi>
Oh, now this is quite an intricate bug
<mwk>
I'm pretty sure 4) is a bug, and will fix it, so the overall problem should be fixed
<Degi>
Thanks ^^
<mwk>
I may also modify 5) to remove duplicated init bits as well, though arguably they shouldn't exist in the first place