01:22 <Flea86> yifei: Have you looked at https://github.com/enjoy-digital/litex/wiki/Hard-core-CPUs

05:21 <yifei> Flea86: seems like the 7000 product line isn't well supported? Thx for the pointer :)

06:20 <Flea86> yifei: No problem

09:38 <tnt> I don't get how litepcie 526a3d05aafcf8877b7cb9f893de82f3bd85a6e4 can ever work ...

09:39 <tnt> _florent_: did you use this on actual hardware ?

09:57 <whitequark[cis]> tnt: curious what the problem is

10:13 <tnt> whitequark[cis]: me too ... I'm looking at s_axis_rq_adapt_x8.v and first issue is almost like if user_reset didn't happen. Because the very first header is passed "as-is" like if s_axis_rq_tfirst was low the whole time.

10:19 <tnt> whitequark[cis]: did you use that core in this configuration sucessfully ?

10:19 <whitequark[cis]> I havent'

11:01 <tnt> "The user application must keep the s_axis_rq_tvalid signal asserted over the duration of the packet. "

11:01 <tnt> The new code introduced in 526a3d05aafcf8877b7cb9f893de82f3bd85a6e4 removed the FIFO that was aggregating data in continuous packets.

12:25 <tnt> Also something weird introduced earlier but tkeep for litepci is 32b but for the xilinx ip it's 8b ... so the top 24b just end up discarded ...

14:49 <tnt> Fixed by https://github.com/enjoy-digital/litepcie/pull/127 . Tested on my hw, but probably should be tested for other combinations too ...