_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> Anyone used PCIe on USP recently ? (DMAReader to be precise)
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<_florent_> yes, what's your issue?
<tnt> Something is wrong with DMAReader (well it's not in DMAReader, it's in the phy) since the cleanup.
<_florent_> Thanks, I'll check to see what is different from the build I do/configuration I used.
<tnt> I'm in x8 gen 3.0
<tnt> I'm trying to inspect the pcie_support thing now, But not sure how to add verilog signals to litescope yet
<_florent_> x8 gen3.0 is also what I've been building recently
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<_florent_> Are you on Ultrascale or Ultrascale+?
<tnt> Ultrascale+
<tnt> ZynqMP EG11
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<_florent_> OK, so same also
<_florent_> Can you share the LitePCIe integration code?
<_florent_> I'll do a test on hardware with a configuration as close as possible to yours
<tpb> Title: self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x8"), - Pastebin.com (at pastebin.com)
<tnt> and then I just have some test module connected to dma0.
<tnt> Is there a way to tap verilog signals ?
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<tnt> _florent_: any luck in reproducing the issue ?
<tnt> _florent_: tkeep is defined as data_width/8 but in the doc it's data_width/32 (and the old code seems to indeed use data_width/32) ?
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<tnt> _florent_: This seems suspicious to me : "AXISTEN_IF_RC_STRADDLE" : True,
<tnt> _florent_: confirmed that was the problem.
<_florent_> @tnt sorry, had to do something else. Good catch thanks!
<_florent_> In the projects I'm testing more regularly, I'm using an generated .xci, so wasn't having the issue...
<_florent_> Sorry for the typo when simplifyng the Ultrascale(+) support and thanks a lot for the feedback/fix!
<tnt> _florent_: well ... all isn't fixed :/
<tnt> This only fixed up to 76c7381ad8d7eab01020fd9bbe0249166535f2a8 (the cleanup).
<tnt> But going to master it fails again :/
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