#litex on 2024-02-02 — irc logs at libera.irclog.whitequark.org

2021-05-24 10:26 _florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex

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12:44 <tnt> Does anyone know how to make the CSR bus larger ? (i.e. more than 32 "devices") ?

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22:31 <CarlFK1> https://github.com/chipsalliance/fpga-interchange-tests/actions/workflows/ci.yml

22:31 <CarlFK1> This scheduled workflow is disabled because there hasn't been activity in this repository for at least 60 days. Enable this workflow to resume scheduled runs.

22:32 <CarlFK1> There are some errors I can probably fix, like "update ubuntu version"

22:33 <CarlFK1> also.. are the resulting bitstreams saved somewhere so I can load them onto an Arty?