_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> Does litex support connecting to unpacked arrays ports (SystemVerilog) when using Instance ?
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<whitequark[cis]> I don't believe migen knows about SV
<tnt> I guess I'm writing a wrapper then :/
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