#litex on 2023-10-27 — irc logs at libera.irclog.whitequark.org

2021-05-24 10:26 _florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex

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13:37 <hve> clock in Litex are confusing. Anyone know how to get the current clk Signal from within a litex module?

13:38 <tnt> ClockSignal()

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13:42 <hve> Is this the same as "self.cd_sys.clk" ??

13:42 <tnt> I think so.

13:43 <hve> I will try, tnx

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14:27 <hve> One more maybe: self.specials += Instance("pwm",p_WIDTH=width,... Instance("pwm", ... Is not a migen value

14:28 <hve> I have added the verilog file using add_source with a "module pwm"

14:56 <hve> Stupid mistake... fixed..

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