<josuah>
but you can also use it from a scrip with `from litex.tools import litex_soc_gen` then instantiate your own derived SoC out of it, to plug more things to it:
<josuah>
class YourSoC(litex_soc_gen.LiteXSoCGenerator):
<josuah>
then when you will build it, you will geet a Verilog file, but nothingwould be built from it.
<josuah>
But... you can also target a board directly, as some cores need non-portable elements to work, and even build it
<josuah>
and integrate the extra cores you need into LiteX instead of integrating LiteX into another project. (both are possible though)
<gurki>
if you already have an existing design it might be easier to integrate some small rv core by hand than to try to integrate everything into a soc generator
<gurki>
the latter is nice and easy until you have custom parts :3
<gurki>
but this probably heavily depends on what you have in front of you :)
<joshua_>
josuah, ha, familiar faces from all over the internet :) I guess I coudl have asked you in the 1b2 discord then!
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<joshua_>
as gurki noted I am currently going to integrate vexriscv by hand for this current design. later I think I do want to integrate things into a SoC generator that will have a bunch of top level ports for custom I/O in my design, and bind those out to register files generated by a SoC generator (it is *very* alluring to have something generate HTML documentation that I can hand to my client!).
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<joshua_>
this current design I need, basically, a UART, a SPI initiator, and two registers for counters that come from logic