10:51 <josuah> > a bunch of top level ports for custom I/O in my design

10:52 <josuah> this can be done by adding a Wishbone module that contains a connector which is the wishbone signals

10:52 <josuah> as if there was an actual "wishbone physical connector", that you will not plug to a cable, but internally in the exported design

10:53 <josuah> the .connect_to_pads() helps!

10:53 <josuah> maybe litex_gen_soc.py has that though...

10:54 <josuah> from 1b2 to here, all in the same boat :]

10:54 <josuah> Unrelated: on Zephyr's zephyr/drivers/serial/uart_liteuart.c:

10:54 <josuah> - litex_write8(UART_EV_TX | UART_EV_RX, UART_EV_PENDING_ADDR);

10:54 <josuah> + litex_write8(UART_EV_RX, UART_EV_PENDING_ADDR);

10:55 <josuah> This fixes the interrupt-driven uart core, it does not provoke a constant interrupt shower either.

11:04 <josuah> I'll pull-request this into Zephyr

11:37 <josuah> https://github.com/zephyrproject-rtos/zephyr/pull/63858

11:37 <josuah> Zephyr is not required to test this as it is hardware dependent