07:19 <stettberger> Hey there! I was redirected here from the #ulx3s channel. I have the goal to build an quad-core RISC-V SoC on an ECP5-85K FPGA (on an ULX3S Board) that I can use to teach students how to build multi-core operating systems. I'm also aware of the litex-linux-on-vexriscv repo, and I took the route to build a system with that repository. And while it

07:19 <stettberger> synthesizes and I can load the bitstream into the device and it shows some boot messages, I was not able yet to find a combination of settings to have a fully working multi-core setup with Linux (which I use as a first benchmark to test the hardware).

07:19 <stettberger> Therefore my question: Does somebody have fully working multi-core RISC-V system running on an ECP5-85K and give me some hints how to achieve the same success?

07:56 <geertu> stettberger: somlo is, but using rocket instead of vexriscv

07:56 <geertu> somlo_: ^

08:37 <stettberger> somlo_: Impressive work with doing the full self-hosting of a rocket core. that is great work!

12:28 <somlo_> stettberger,geertu: thanks! :)

12:29 <somlo_> to be super pedantic, if you want to run a linux distro you need the fpu-enabled version of rocket, and only one such core will fit on the ecp5-85k

12:30 <somlo_> you can have two (not sure if 4 will fit, can't quite remember) if you give up on the fpu -- still able to run linux, but not a distro kernel

12:31 <somlo> there's vexriscv-smp -- it's 32-bit, so might fit 4 cores, and *should* be able to also run linux on it. It's just not something I have tried myself

12:33 <geertu> somlo: Unfortunately no standard Linux distro supports 32-bit, so that's a good reason to use rocket instead.

12:34 <geertu> I guess the -85K does vex-riscv multi-core. My -25K doesn't (and also no rocket :-(

13:07 <zyp> isn't naxriscv also a decent alternative?

13:13 <geertu> zyp: Perhaps. I haven't tried all possible RISC-V cores yet (not to mention non-RISC-V like microwatt and J-core)

14:47 <stettberger> somlo: So yeah, rocket dual core does not fit, but a vexriscv_smp with four cores still fits. So that would be the right choice, however, currently I'm stuck in the Linux boot process. So probably, I have to file a bug there. But I wanted to ask around if it is just a me problem, beforehand.

14:52 <somlo> stettberger: rocket dual "linux" core (which now includes FPU) won't fit, but dual "medium" should. The latter has MMU and S-mode, but no FPU, and it can run linux (I used to have bbl emulate the fpu for a while, but bbl is now deprecated and opensbi refuses to support fpu emulation in m-mode, probably for good reason :)

14:54 <somlo> either way, a 32-bit cpu is probably better for a "write-your-own-os" class project: 64-bit has more levels of indirection in page tables, and generally more "overhead" but without additional opportunity for learning how to write an os or how an os works

14:56 <somlo> stettberger: so I guess you're really better off with vexriscv-smp for your goals (as much as I'd love to have more people play with *my* --rocket-based, 64-bit_-- pet project :P)

14:57 <somlo> I'd check github.com/litex-hub/linux-on-litex-vexriscv as a starting point; vexriscv is by far the more "popular" litex cpu option, so you should have no trouble finding help on how to get it running on your board

15:02 <stettberger> that is currently my starting point there. But already the single core vexriscv_smp was not booting with the prebuild buildroot. I already have a freshly built linux around, but I'm missing an sdcard reader to flash it atm

15:02 <stettberger> Yeah, for building your own OS, 32-bit is more than enough horror

15:03 <stettberger> Currently, we are doing this with IA-32 (while some colleagues switched to AMD64, because... i don't know)

15:04 <stettberger> My hope is that I can remove the IA-32 Segmentation model from my yearly schedule....

15:32 <stettberger> zyp: I had a look at naxriscv now. Can you build a multicore system from that?

15:33 <stettberger> But in the end, I do not have the requirement to have a faster core by out-of-order execution, but a system with MMU, 4 cores and S mode