01:32 <joshua_> Hi, all. I'm trying to glue a small RISC-V core to an existing design that I have -- my goal is to have a module that has clock and reset pins, a set of SPI controller pins, a set of UART pins, and a few other inputs that I'm hoping to plumb into the core as CSRs (or MMIO registers, or whatever). I was thinking that the way I'd want to do this was to have LiteX generate a SoC for me.

01:32 <joshua_> (I was particularly interested in the idea that I could get LiteX to generate register docs for me!)

01:33 <joshua_> The situation in https://github.com/enjoy-digital/litex/wiki/Export-Your-Core-SoC-To-Verilog is not fantastic, though :-) Does anyone have any suggestions for how to accomplish what I want? (In exchange, I'll document it on the wiki if I get it working!)