08:13 <sensille> hm. timing violation in s6rgmii

08:35 <sensille> is there some magic in cycles=256 in LiteEthPHYHWReset? with a smaller counter constraints are met. i could break it in 2 smaller counters, though

08:52 <sensille> ah: "The reset

08:52 <sensille> pin must be asserted for at least 2.0 µs"

08:52 <sensille> -> 250 cycles

08:54 <sensille> so i'll add a prescaler

09:20 <sensille> disregard that, i'm just reading the timing report wrongly

09:57 <sensille> still, without that counter timing is met :-/