_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tpw_rules> _florent_: i'd really like to move some code out of https://github.com/enjoy-digital/litex/blob/7a7c74faa9b02f70ebb6e0f8a08abdc7411a368b/litex/soc/cores/cpu/vexriscv_smp/core.py into the vexriscv smp data module to avoid circular issues and foster easier generation. how can i best coordinate cross-repo PRs like that?
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