_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> python again ... now I ran into https://github.com/enjoy-digital/litex/issues/1716
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<sensille> _florent_: liteeth and block ram again ... do you think it reasonable/feasible to block CPU reads to the tx buffers as long as the core transmits?
<sensille> reducing the number of read ports to one would help my project significantly
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<sensille> even better, i don't think i have to read back the txbuf at all
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<tich> Good Day How do I generate Verilog code from a LiteX defined board
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