00:45 <zyp> did you do a pci rescan?

01:04 <nwest> didn't know that as a thing to do, but I just tried `echo 1 > /sys/bus/pci/rescan` and no change

01:13 <nwest> aha, I'll need to work out the exact sequence, but it's a bit of a crapshoot now. the rescan is an important bit, but there's some order of not having module loaded, load gateware, load module, rescan that does seem to work but is sensitive

01:13 <nwest> thanks

01:16 <nwest> the confounding info here is I'm operating over a TB3 extension board, so cable gets plugged/unplugged between some uses. It will consistently work if I do

01:16 <nwest> 1) rmmod

01:16 <nwest> 2) load gateware

01:16 <nwest> 3) init / load module

01:16 <nwest> 4) rescan

01:36 <j4cbo> so, i'm using litex for a very small system (iCE40, SERV softcore) where I really don't need anything the litex BIOS provides but will instead just put all my code (<4kB) in block RAM

01:36 <j4cbo> is there a way to get the litex Builder to compile it for me as part of building the SoC, the way it normally builds the BIOS, or do i need to just compile my code myself and use compile_software=False and soc.initialize_rom()?

03:26 <nwest> Also seems to reliably work if I

03:26 <nwest> 1) rmmod litepcie before unplugging

03:26 <nwest> 2) load gateware

03:26 <nwest> 3) init.sh (insmod)

03:26 <nwest> no rescan required. Any ideas if there's some hotplug detach events that could be caught to handle this unplug nicer?