_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Guest86> Does there exist an example or documentation somewhere on how to use the 'write' function for the AXILiteInterface in litex>soc>interconnect>axi>axi_lite.py ?
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