#litex on 2022-08-28 — irc logs at libera.irclog.whitequark.org

2021-05-24 10:26 _florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex

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16:27 <absurdfatalism> Hi folks I have a very basic litex_soc.py script that sets up a VGA pmod and video generator VGA timing signals

16:27 <absurdfatalism> https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/litex_soc.py

16:27 <absurdfatalism> I connect it to a VHDL module I wrote that using video timing signals to drives the VGA output, chasing the beam etc

16:27 <absurdfatalism> But now I want to introduce a frame buffer, using Litex provided frame buffer stuff

16:27 <absurdfatalism> I'd love the keep the VGA pmod setup as is

16:27 <absurdfatalism> And just replace the chasing the beam setup with like a AXI bus to-from some frame buffer module

16:27 <absurdfatalism> Where I can just read+write the AXI bus to get/set pixels in the frame buffer memory

16:27 <absurdfatalism> (and all the reading for display+vga timing, etc is all handled in frame buffer I guess?)

16:27 <absurdfatalism> Is there a good example I can use that would show just basics

16:27 <absurdfatalism> frame buffer + axi + <insert your code here> essentially ?

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