<minute>
i have tested the following adjustments now on bpi cm4: 1. bump sdio to 200mhz from 25mhz, and set voltage to 1v8. 2. remove dram-access-quirk on sdio. this improves downstream speed up to 54mbit/s here (on both 5ghz and 2.4ghz). also, the random stalls seem to be gone
<minute>
next i will try the out-of-tree driver to compare
<minute>
xdarklight: so it sounds like i'm getting similar speeds to your s905x3 setup now
<minute>
removing the dram-access-quirk didn't make much difference btw
<minute>
while i'm at it, is SCDC (for hdmi) still broken nowadays or does it work @ a311d?
<narmstrong>
minute: it should work
<narmstrong>
it has been fixed long time ago
<minute>
narmstrong: oh cool, thanks. i will remove a patch disabling that then that we are carrying around
<narmstrong>
lvrp16: I've been trying to add cottonwood boards to u-boot mainline to enable EFI Capsule Update like I just did for lafrite, but while enabling the stuff SPI Flash doesn't work anymore _after_ enabling USB Gadget, you disabled SPI flash in your u-boot tree, did you encounter the same issue ? did you find why ? So far I have no clue why USB Gadget would affect SPI Flash
<lvrp16>
narmstrong: do you have eMMC attached? I disabled SPI flash so users don't tamper with the NOR contents accidentally. It should not affect gadget. I will test on my end tomorrow. I am currently working on the RTL8211F losing interrupts.
jacobk_ is now known as jacobk
<narmstrong>
lvrp16: yes I have, enabling emmc doesn't affect spi flash, I'm tracing what could be the issue...
<lvrp16>
eMMC and NOR pins are muxed. I enable 8 IO for eMMC and disable NOR in my branch.
<narmstrong>
yeah I saw that
<lvrp16>
The CM is working incredibly well btw.
<lvrp16>
I copied the BPI CM4 and reworked the bootloader. Sad thing though is that if I shutdown EE domain, it seems AO domain dies as well.
<lvrp16>
So no super power optimization for standby.
<narmstrong>
neat, perhaps another CM that could ship with the mnt reform laptop ?
<lvrp16>
Our is slightly different. No RF onboard. It has SDIO on FPC connector.
<narmstrong>
ok so it's really DFU that breaks, if I to ums, spi flash still works
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<narmstrong>
something weird's happening...
<narmstrong>
lvrp16: ok I found, when probing the spi flash on G12 with mode=0, the hw just fails, while on GXL it still works
<lvrp16>
Mode is 1 no?
<lvrp16>
By default if my memory is correct.
<narmstrong>
with DM_SF, mode is taken from DT
<narmstrong>
but you can still use the legacy spi_flash_probe()... I just updated dfu_sf with the proper code and it works now
<minute>
heh, suspend/resume almost works on the a311d
<minute>
how could one fix the clock rate after resume?
<minute>
for example > Big core clk resume rate 50000000
<minute>
and the display updates extremely slowly, and several IP cores fail, after USB re-init the system freezes
<minute>
turning off all big cores before sleep helps, but it still freezes and somthing is still wrong with DSI clocking (i can see the panel update at very low freq)... so perhaps those clocks have to be reset after resume?
<narmstrong>
Yes probably, but for display everything is shut down then reconfigured on resume, the pain point are clocks changed by the suspend firmware, we don’t really know what’s changed and it could be different among different firmware revisions
<minute>
narmstrong: would it be possible to reset the whole clock tree? :3
<minute>
if it wouldn't freeze i could at least make some before/after diffs...
<xdarklight>
minute: cool! the out-of-tree driver is "only" 50% faster than what we have upstream - I still call it a success ;-). most important thing is to have the random stalls fixed
<minute>
xdarklight: i will dogfood this a bit more over the next days... i deployed an update for our systems today where i bumped the clock to 100mhz. wanna see if that's stable for a few days