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<get0rix[m]>
Hi! Silly question maybe, but what is the shortest pulse Glasgow can produce on IO? Looks like self.pin.o.eq(~self.pin.o) generates 24MHz strobe with pulse around 21ns and this is the limit. Just pushing boundaries for my glitch setup 😄
<whitequark[cis]>
get0rix: this is the shortest you can reliably go without using a PLL
<whitequark[cis]>
in theory you should be able to go as low as 10 ns, possibly down to single nanoseconds
<whitequark[cis]>
I have a cursed idea I could test
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<get0rix[m]>
Hi! Silly question maybe, what is the shortest pulse Glasgow can produce on port IO? Looks like self.out.o.eq(~self.out.o) generates 24MHz strobe wth pulse width around 21nm, while I would expect it to be 48MHz as it is set by sys_clk_freq=48e6 with pulse width around 10nm. Clearly I am missing something. Thanks for any hints!
<get0rix[m]>
* Hi! Silly question maybe, what is the shortest pulse Glasgow can produce on port IO? Looks like self.out.o.eq(~self.out.o) generates 24MHz strobe wth pulse width around 21nm, while I would expect it to be 48MHz as it is set by sys_clk_freq=48e6 with pulse width around 10nm. Clearly I am missing something. Pushing my glitch setup to the limit. Thanks for any hints!
<whitequark[m]>
I replied to you on Matrix, unfortunately the bridge is having issues at the moment
<get0rix[m]>
Matrix? sorry, looks like I am behind everywhere 😄
<whitequark[m]>
we have a Matrix channel as well as the Discord one
<joshua_>
I am now curious as to how cursed we are talking here
<get0rix[m]>
Thanks Catherine! I will start looking for Morpheus to get the pill for Matrix 😄
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<josHua[m]>
the bridge does seem to be working between IRC and Matrix
<josHua[m]>
(libera #glasgow)
<fishmonger[m]>
You can cheat a bit, Go to https://glasgow-embedded.org/ -> Community -> irc logs. The IRC bridge is working.
<josHua[m]>
Discord -> {matrix,IRC} seems to be working as well, just {matrix,IRC} -> Discord is wedged at the moment
<get0rix[m]>
What do you think, I am lazy??? I will install Matrix client and login there 😄 😄 😄
<josHua[m]>
well, I am lazy, and use IRC because I cannot figure out Matrix 🙂
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<getorix[m]>
yep, no biggie, pretty straight forward :D
<whitequark[m]>
PSA: I just fixed an important safety issue (https://github.com/GlasgowEmbedded/glasgow/issues/552) where reconfiguring the FPGA with a new bitstream with Vio voltage on would cause all pins to be momentarily driven to a strong high level; everyone should pull from the repository and run `glasgow flash`
<whitequark[m]>
esden (@_discord_269693955338141697:catircservices.org) can you use the crowdsupply update mechanism to mention this?
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<whitequark[m]>
and if you updated correctly you should see a message about "API level 3"
<getorix[m]>
Catherine: I have been playing with your pulse snippet, spent time digging into amaranth docs etc. Correct me if I am wrong, but as I understand the pulse is a result of physical delay during signal propagation thought d1-d4 trigger LUTs? Like what is supposed to happen instantly in theory, still requires fraction of time in real world. Did I get it right?
<getorix[m]>
* trigger LUTs exploited by xor logic? Like
<whitequark[cis]>
basically yes
<getorix[m]>
wow, thanks!
<whitequark[cis]>
i mean the theory says the same as the practice here
<whitequark[cis]>
a LUT4 is a real physical unit
<whitequark[cis]>
it's just that synchronous logic uses a certain model of the world (zero delay model) that is valid under certain conditions (all timings met)
<whitequark[cis]>
i am violating the timings, or rather their associated restrictions, by not registering the output of a comb circuit
<getorix[m]>
I am new into FPGA programming, that is why I thought all signals change same time if they are connected (what I call theory) :)
<whitequark[cis]>
this is well known to potentially cause glitches. here, i can control the glitch enough to make it desirable
<whitequark[cis]>
I see
<whitequark[cis]>
yeah, I am exploiting the areas where the simple model no longer works
<getorix[m]>
it works pretty cool, and by changing the length of cascade it is possible to fine tune it further :)
<getorix[m]>
s/cool/good/
<getorix[m]>
* it works pretty good, and by changing the length of trigger cascade it is possible to fine tune it further :)
<whitequark[cis]>
somewhat, yes
<whitequark[cis]>
note that wires also add finite time
<whitequark[cis]>
so making the cascade too large will make it slower than youd expect looking at LUTs alone
<getorix[m]>
yep, but seems good enough to control EMFI pulse width
<whitequark[cis]>
this should kick in at 7 stages or so
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<joshua_>
hm, you could presumably also get better pulse characteristics by using the LVDS outputs
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<theorbtwo[m]>
The "lvds" pins are just raw fpga pins, so maybe, but also danger.
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<esden[m]>
whitequark (@_discord_182174208896401419:catircservices.org) I am adding the necessary text to the update right now.
<tomkeddie[m]>
whitequark (@_discord_182174208896401419:catircservices.org) am looking to buy some of those Ethernet boards in my taobao order next month, wondering if you're still planning to add support? I guess long term we'll need our own add-on pcb.
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