dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
<rwmjones> somlo's fosdem talk from 2023 is trending
<rwmjones> somlo: a real danger to hardware is a "kill signal", a long, unlikely series of bits which kills the chip
<rwmjones> (so you send this just before you invade etc)
<rwmjones> FPGAs are just as vulnerable to this as everything else
<somlo> rwmjones: a kill switch is equivalent to a "denial of service" attack, your hardware ends up dead. At least you *know* :)
<somlo> but it can get worse, your cpu could be silently undermining you with a "privilege escalation" embedded in silicon, where your computer keeps appearing to work while cooperating with your attacker behind your back
<somlo> with an FPGA I can't mitigate against the kill switch, but (with a self-hosting, sources-all-the-way-down gateware+software stack) I can protect against the privilege escalation
<rwmjones> oh for sure
<rwmjones> apparently there are verification services that will examine your hardware with a big microscope to check the implementation matches the RTL
<rwmjones> I imagine extremely expensive services
<rwmjones> I did a talk (internal at Red Hat) about using frama-c, ACSL, compcert, etc to go from source level to hardware
<rwmjones> verified all the way
<somlo> some of the "privilege escalation" silicon attacks I mentioned in my fosdem slide deck are the A2 trojan (https://web.eecs.umich.edu/%7Etaustin/papers/OAKLAND16-a2attack.pdf) where all they need is cca. 20 extra transistors and one capacitor, carefully connected to the rest of your asic cpu, to allow a pre-determined sequence of unpriv. instructions to flip a bit (e.g., your ring/privilege flag)
<somlo> I'd expect 20 transistors to be rather hard to spot in a die shot :)
<somlo> then there's switching dopant polarity in "select" transistors to make e.g. a random number generator more predictable: https://pdfs.semanticscholar.org/6407/ebd0a24026e4dad84bcc10fbba165d521a50.pdf
<somlo> that'd be altogether impossible to spot in a die shot
<somlo> my "defense" is predicated on the FPGA designers and the foundry that made it having no idea what I'll be using it for, *later* :)
<somlo> so they can't fine-tune a privilege escalation silicon attack tailored to my (future) bitstream.
<somlo> and I'm currently studying vlsi design (the uni where I work lets me take free classes) to see if there's anything more that could be done (not too hopeful, but at least I'm learning something fun) :)
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<rwmjones> agreed
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