<davidlt[m]>
Intel does in a different way compared to AMD
<davidlt[m]>
There are actually multiple Intel or TSMC solutions
<davidlt[m]>
It's interesting that Intel is using "iCXL"
<davidlt[m]>
I think in TSMC language Intel is doing CoWoS (chip on wafer on substrate). There are no logic in the base tile, basically a bunch of wires to high-bandwidth low-latency.
<davidlt[m]>
I think Intel also had EMIB "embedded bridge" which was a small silicon doing the same (instead of a full base substrate)
<davidlt[m]>
AMD for 3D stuff is probably using TSMC SoIC (WoW or CoW) for the 3D Cache stuff
<davidlt[m]>
It's really fun to see that new major advancements is now packaging :)
<davidlt[m]>
Multiple chiplets and 3D stacking is now an option, just need to make sure you control voltages, thermals and power consumption of the interconnect.
<davidlt[m]>
Moving data is really expensive power wise.
<davidlt[m]>
But chip costs are huge these days. Ridiculous.
<davidlt[m]>
I am sure the price for N3, or N3E, or anything newer will continue to increase.
<davidlt[m]>
TSMC N3* family should be interested with Fin Flex.
<davidlt[m]>
IIUC you can now mix high-efficiency, performance, very high performance bits in one silicon part.
<davidlt[m]>
You don't need to wait and use a special optimized variant of N3 for that.