dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
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<rwmjones> morning
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<fuwei_rh> Hi all
<fuwei_rh> for podman support on riscv, we need criu
<fuwei_rh> but , it seems we are missing this support , dose anyone have any info about it?
<rwmjones> so this needs kernel support ..
<rwmjones> no idea if that is arch-specific or not
<fuwei_rh> criu is missing kernel support ?
<rwmjones> since it supports checkpointing, maybe something to do with registers etc
<rwmjones> btw checkpointing is generally an optional feature for containers, so maybe podman can be compiled without this?
<fuwei_rh> yes, it supports checkpointing
<rwmjones> I mean, checkpointing as a feature is quite niche
<rwmjones> so maybe you can compile podman w/o the support?
<fuwei_rh> rwmjones: great thanks , let me have a try
<rwmjones> dwalsh would be the expert here
<rwmjones> looking at the spec file, it looks like criu is bundled
<rwmjones> ?
<fuwei_rh> we are trying to local the problem that which package requires criu, then see if we can skip or workaround it
<fuwei_rh> the runtime of podman is missing criu
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<rwmjones> fuwei_rh: is the problem that the 'criu' (ie. Fedora) package is not available? I'm not sure I understand the issue
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<fuwei_rh> rwmjones: yes, criu is not available for riscv, need some porting
<fuwei_rh> we can not build criu rpm package on riscv, even debian haven't got this package built
<rwmjones> https://criu.org/Checkpoint/Restore - looks very arch-specific
<rwmjones> "Core parameters of a task (such as registers and friends) are being dumped via ptrace interface"
<rwmjones> davidlt[m]: on the unmatched, how is the blue sleeve that holds the heatsink to the cpu attached? is it possible to remove it?
<rwmjones> i can't seem to find a way to get it off short of cutting it
<fuwei_rh> I have got some help from Carlos
<fuwei_rh> we are trying to rebuild runc to skip "Requires: criu"
<rwmjones> I'm sure that's the right approach, criu of containers is a somewhat niche feature
<fuwei_rh> thanks
<rwmjones> basically it only applies if you're using kubernetes and need to migrate containers between nodes without stopping & starting them, it's quite unusual
<fuwei_rh> ah, OK, got it , thanks :-)
<fuwei_rh> we are using ifnarch now
<davidlt[m]> rwmjones: I think it's glued
<davidlt[m]> yeah, criu doesn't support riscv
<davidlt[m]> crun has --disable-criu
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<davidlt[m]> crun.spec looks intresting
<rwmjones> davidlt[m]: nujive is up again
<rwmjones> I just removed the cpu fan to try to improve airflow
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<davidlt[m]> That's what I do
<davidlt[m]> What temps did you get during heat wave?
<rwmjones> I thought I'd checked it, but I can't see that in the scrollback now
<rwmjones> the room itself was 40C, so ..
<fuwei_rh> rwmjones: we rebuilt runc, and works well
<davidlt[m]> isn't default runtime crun these days?
<fuwei_rh> rwmjones: podman rpms packages have been built (f36/rawhide)
<fuwei_rh> davidlt[m]: for my env , it depends runc
<davidlt[m]> I checked my system and default is crun for OCI runtime
<fuwei_rh> davidlt[m]: I am not familiar with podman, but for my F36, this is runc, but not crun
<fuwei_rh> I am confused with crun and runc :-(
<fuwei_rh> but it works now
<davidlt[m]> what? crun is a newer one and based on C, while runc was the first reference implementation of OCI runtime and used Golang
<davidlt[m]> They found out that Golang as a language IIRC has some limitation and thus at some point runc (C implementation) happened
<davidlt[m]> rwmjones: there are a several Fedora/RISCV Koji instances now out there in the world, we should figure out what to do with all that
<fuwei_rh> maybe Carlos can answer this question , but I just try to solve the dependency problem :-)
<fuwei_rh> davidlt[m]: we did build a lot of goland packages for podman :-)
<fuwei_rh> s/goland/golang
<fuwei_rh> davidlt[m]: rwmjones for now, we are working on mass rebuild for rawhide, and stop working on f36,
<davidlt[m]> fuwei_rh: IIUC you are doing stuff for StarFive, D1 and similar?
<davidlt[m]> Like I am not planning on supporting D1 until that is somewhat resolved upstream
<davidlt[m]> I know there is StarFive Koji, and there is another Koji in China (openkoji), and there might another one too, just don't recall it
<fuwei_rh> not for now, I am working on qemu , but just play with JH7100 and D1,
<davidlt[m]> Ah cool, as those boards most likely will not get support from me
<davidlt[m]> JH7100 is pretty much dead, all efforts are for JH7110, which most likely will get be supported
<fuwei_rh> I did make D1 image last week , just because someone want an image for D1, :https://openkoji.iscas.ac.cn/pub/dl/riscv/Allwinner/Nezha_D1/images-release/Fedora/
<davidlt[m]> D1 might be supported at the end (there are some patches based on alternative errata framework)
<fuwei_rh> true , JH7100 is dated
<rwmjones> davidlt[m]: yup
<fuwei_rh> I am waiting for JH7110
<fuwei_rh> I got a K510 too
<davidlt[m]> Sadly Beagleboards got delayed
<fuwei_rh> yes
<davidlt[m]> I recall K510 announcement, but not sure if there are any boards
<davidlt[m]> The most interesting boards to support would be PINE64 RISC-V board, StarFive new board with JH7110 and two new BeagleBoards
<fuwei_rh> but I am very looking forward to BeagleV (there are two this year)
<davidlt[m]> PINE64 and BeagleBoards are bound to be quite popular
<davidlt[m]> Ah yes, and a new SiFive board
<davidlt[m]> Yeah, they were supposed to be announced in Embedded World, but I think chip shortage delayed everything
<davidlt[m]> Which might be a problem for any board these days
<davidlt[m]> I mean, until the boards are built never know if the product will happen :)
<rwmjones> k510 is based on an andes core?
<davidlt[m]> Yes
<fuwei_rh> yes
<davidlt[m]> Well, it's Taobao thus not the best place to order (at least for me)
<fuwei_rh> I have bought one , but have not tried
<davidlt[m]> These are niche boards (exception is D1)
<fuwei_rh> I am not sure if they sale them abroad
<davidlt[m]> D1 is annoying. It's cheap, kinda popular, but not according to the standards
* rwmjones wonders if my aliexpress password will work on taobao
<davidlt[m]> I hope it goes EOL sooner than later :)
<davidlt[m]> I don't even want to deal with customs :)
<davidlt[m]> and wait two months to get it
<rwmjones> apparently not
<fuwei_rh> there is a new C910 dev board on the way
<rwmjones> I thought they were the same company somehow
<davidlt[m]> Yeah, that one I am waiting for
<davidlt[m]> But I am not sure how compliant to the RVI standards it will be
<davidlt[m]> PINE64 shows the pictures of their SBC, that one will be quite nice and probably soonish
<fuwei_rh> D1 is from Allwinner , which using C906 core from thead, C910 Soc is from thead directly
<davidlt[m]> Yeah, but that doesn't mean that it's compliant
<davidlt[m]> Allwinner didn't design the C906 cores in D1, and C906 are not compliant to RVI standards
<fuwei_rh> same as 906 (for standards)
<davidlt[m]> And that's twice bad
<fuwei_rh> I mean c910 is a upgrade version of 906
<davidlt[m]> I mean to get it working someone is using alternatives framework for erratas
<davidlt[m]> Yeah, but we don't know what they cooked into those cores this time
<davidlt[m]> It might be they fixed those issues, or maybe not, maybe created more issues
<fuwei_rh> but the patch for 906/910 has upstreamed
<davidlt[m]> Hardware and software teams need to talk before chip happens to avoid these kind of nightmares
<davidlt[m]> I don't think so
<davidlt[m]> I think the last version was July 7th
<davidlt[m]> [PATCH v7 0/4] riscv: implement Zicbom-based CMO instructions + the t-head variant
<fuwei_rh> I meant "svpbmt"
<fuwei_rh> CMO hasn't done yet,
<fuwei_rh> yes
<davidlt[m]> There is: [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types
<davidlt[m]> I don't think Palmer pulled it yet
<davidlt[m]> Ah, he did
<davidlt[m]> Not sure if that's for 5.19 or 5.20
<fuwei_rh> I has been told , svpbmt has been upstreamed :-)
<fuwei_rh> so C910 is not a big problem now , is 12nm , can run up to nearly 2GHz
<fuwei_rh> JH7110 is 28nm, can run up to 1.2G ~ 1.5G
<davidlt[m]> Checked, v5.19 will have ERRATA_THEAD_PBMT
<davidlt[m]> By the problem I mean how they are following standards, not the process node or freq.
<davidlt[m]> C910 should be cool as long as they don't break RVI standards
<fuwei_rh> C910 has same design on svpmbt with 906
<davidlt[m]> and that's annoying
<fuwei_rh> s/svpmbt/svpbmt
<fuwei_rh> for their freq or performance, hope they can be better builder for our koji
<davidlt[m]> That's true
<davidlt[m]> OoO + proper cache subsystem design + high freq would be a nice upgrade