11:29 <maikmerten[m]> after toying around with some tutorials I found that for me, the best way to get started is... the "Getting started" section in the official docs. I now have a blinking HX8K breakout board in front of me.

11:53 <maikmerten[m]> still very much confused about platform.request("led"): This returns a single pin ("flipped(<Pin: Pin.Signature(1, dir='o'), path=('led_0',), name='led_0', o=(sig led_0__o)>)") and I wonder how to get access to all eight LEDs on the board

12:47 <zyp[m]> you just repeat that call as many times as you need

12:48 <zyp[m]> or you could do e.g. platform.request("led", 3) to get a specific one

12:48 <zyp[m]> the LEDs are defined as individual resources in the platform and therefore have to be requested one by one

12:49 <maikmerten[m]> can one somehow combine the single-bit signals to one 8-bit signal?

12:50 <zyp[m]> you could do something like leds = Cat(platform.request("led", i).o for i in range(8))

12:51 <maikmerten[m]> ah, great!

12:54 <maikmerten[m]> (works wonderfully, thanks)

15:30 <maikmerten[m]> I've seen several examples where a component inherits from "wiring.Component". Is there a reason why one wouldn't import wiring stuff via "from amaranth.lib.wiring import Component, In, Out" and then inheriting from "Component"?

15:54 <Wanda[cis]> amaranth.lib in general is kinda designed to be imported as modules, because it doesn't have a policy of not colliding names with amaranth.* and there are already a few (like Const vs data.Const)

15:55 <Wanda[cis]> but ultimately it is your choice; there are no collisions in amaranth.lib.wiring

15:55 <maikmerten[m]> ah, thanks for elaborating!

18:20 <purdeaandrei[m]> Why could I be getting a BrokenTrigger exception? I don't have any `async for` loops

18:20 <purdeaandrei[m]> All I have is something like:... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/BAGtacEALhxiQwrupMIbWHXo>)

18:22 <purdeaandrei[m]> this is inside a loop, but not inside an async for loop so the trigger combination should be re-created every time

18:23 <whitequark[m]> a trigger is considered broken iff the trigger activates (the condition is met) but the process isn't waiting on the trigger

18:24 <whitequark[m]> by chance, is _signal changing at the exact same moment self._debounce_time expires?

18:26 <purdeaandrei[m]> possible, if I adjust _debounce_time a tiny bit, it goes further

18:27 <purdeaandrei[m]> the await that I see in the backtrace, is that the trigger that is broken?

18:27 <whitequark[m]> I don't know what you're seeing in the backtrace

18:27 <whitequark[m]> since I don't have the backtrace in front of me, can you post it?

18:28 <purdeaandrei[m]> this is my whole snippet

18:28 <purdeaandrei[m]> i'm trying to make something that looks like a custom trigger

18:29 <whitequark[m]> sorry, I still can't answer the question about a backtrace without seeing a backtrace

18:30 <purdeaandrei[m]> https://pastebin.com/4iedCrVS

18:30 <purdeaandrei[m]> this is an example of my backtrace

18:32 <purdeaandrei[m]> is it a problem if it changes at the same time?

18:34 <purdeaandrei[m]> I added a comment to show which line the backtrace is pointing to

18:37 <whitequark[m]> it should not be; I think this is a defect in the simulator implementation

18:37 <whitequark[m]> and yes, the line you highlighted is the trigger that gets broken

18:37 <whitequark[m]> can you file a minimal example as an Amaranth issue please?

18:53 <_whitenotifier-1> [amaranth] purdeaandrei opened issue #1508: Broken Trigger when for TriggerCombination delay/changed expires at the same time - https://github.com/amaranth-lang/amaranth/issues/1508

18:53 <purdeaandrei[m]> https://github.com/amaranth-lang/amaranth/issues/1508

19:29 <purdeaandrei[m]> is there a way I can find out the current simulation time? like $realtime in verilog?

19:30 <Wanda[cis]> not yet (there is a pending RFC that will add it)

19:31 <Wanda[cis]> oh fore

19:31 <mwkmwkmwk[m]> not yet; there is an accepted RFC that will add one

19:58 <whitequark[m]> there's even a partial implementation

20:00 <vegard_e[m]> I'm writing tests for it now

20:00 <whitequark[cis]> (note that purdeaandrei can't see your responses since i still haven't repaired the bridge)

20:38 <zyp[m]> that's why I wrote it on discord

21:04 <zyp[m]> tests done, just remains to put it to use now

21:11 <whitequark[cis]> the agenda for the monday meeting is RFC #73 "Stricter connections"

21:42 <Wanda[cis]> for the record I will be on a train with spotty internet coverage during tomorrow meeting