03:14 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark pushed 2 commits to main [+1/-1/±11] https://github.com/amaranth-lang/rtl-debugger/compare/39d7507ed8f3...324949c45ec0

03:14 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark 906d33f - Log latency of CXXRTL server commands.

03:14 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark 324949c - Reimplement Reference Items / Query Interval using the new approach.

07:50 <Wanda[cis]> ohh py3.13 is out

13:25 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark pushed 1 commit to main [+1/-0/±13] https://github.com/amaranth-lang/rtl-debugger/compare/324949c45ec0...ede2a3dd6999

13:25 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark ede2a3d - Implement observer-based debug item value display.

13:38 <jorolf[m]> Looking at lib.fifo.FIFOInterface, wouldn't it make sense to change the read and write ports to use lib.stream?

13:39 <whitequark[cis]> there's an undocumented stream adapter already

13:39 <whitequark[cis]> ideally the FIFOs would be fully stream based, but that's more tricky than it looks

13:39 <jorolf[m]> whitequark[cis]: Where would that be?

13:41 <jorolf[m]> FIFOInterface.w_stream? 🤔

17:38 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark pushed 2 commits to main [+4/-1/±11] https://github.com/amaranth-lang/rtl-debugger/compare/ede2a3dd6999...a9492ad86dc9

17:38 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark f23addd - Factor out debug session management.

17:38 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark a9492ad - Implement watch list management.

17:45 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark pushed 1 commit to main [+1/-0/±5] https://github.com/amaranth-lang/rtl-debugger/compare/a9492ad86dc9...de28e8a99dc4

17:45 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark de28e8a - Implement watch list management.

18:43 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark pushed 1 commit to main [+0/-0/±6] https://github.com/amaranth-lang/rtl-debugger/compare/de28e8a99dc4...8ddd6976969f

18:43 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark 8ddd697 - Implement configurable radix.

18:45 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark pushed 1 commit to main [+1/-0/±6] https://github.com/amaranth-lang/rtl-debugger/compare/8ddd6976969f...7d7fe679963f

18:46 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark 7d7fe67 - Implement configurable radix.

18:48 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/rtl-debugger/compare/7d7fe679963f...4ea4944cc614

18:48 <_whitenotifier> [amaranth-lang/rtl-debugger] whitequark 4ea4944 - Use small caps to approximate look&feel of VS Code native tree view headers.

21:36 <John_K> hey folks, I'm trying to implement my first amaranth project and have been having a bit of trouble determining the newest / best way to connect everything together. I'm currently requesting resources from a platform object in my enumerate function, but this seems to be impossible to do in Simulation since the simulator class hard codes platform to

21:36 <John_K> None

21:37 <John_K> I'm implementing a 4-bit bidirectional bus with a unidirectional clk and control line

21:39 <John_K> https://gist.github.com/John-K/488b2fed707917871795f015e91709c3

21:40 <John_K> would welcome any advice on how to deal with the bidirectional signals better as well

21:48 <zyp[m]> first of all I'd make the data signals one 4-bit signal rather than four independent single bit signals each

23:02 <John_K> well, it can operate in 1 or 4 bit mode

23:03 <John_K> rather, it starts in 1-bit, then switches to 4-bit. But that should still be possible as one 4-bit signal

23:08 <duskwuff[m]> I'd highly recommend looking at the Glasgow QSPI controller - there's a lot of thematic similarities

23:08 <duskwuff[m]> https://github.com/GlasgowEmbedded/glasgow/blob/main/software/glasgow/applet/interface/qspi_controller/__init__.py

23:09 <duskwuff[m]> ignore the non-gateware bits (QSPIControllerInterface and QSPIControllerApplet)

23:54 <John_K> I had originally used that as inspiration, but then couldn't follow directly because of the Glasgow Ports that are used

23:54 <John_K> it has been a bit confusing to look at pads vs ports vs grabbing stuff from platform to figure out what pins to connect up to the logic

23:55 <John_K> I settled on platform as it seemed the cleanest, but then I can't simulate