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<RobertJrdens[m]>
Hello! Anyone aware of any open EtherCAT slave/master impl on FPGA, preferrably in amaranth?
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<whitequark[cis]>
not a complete one
<whitequark[cis]>
I have a small prototype of an Ethernet endpoint in Glasgow, but it's probably insufficient for what you want
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<RobertJrdens[m]>
Ah right. Completely slipped my mind that an ethernet core is a prerequisite...
<whitequark[cis]>
I've put a lot of work into building reusable stream-based cores (also currently in Glasgow) but it's held up by a bunch of edge cases
<whitequark[cis]>
I'd love to have several standard cores available in amaranth-stdio at last, but getting them to the usual level of quality is proving harder than I'd thought
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