<Guest96>
I am using an example where trying to add verilog module as instance. Apparentlyit requires some platform i.e., ICEBreakerPlatform. is it possibel to add file s without using some external platform
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<zyp[m]>
there's two sides of adding a verilog module as an instance
<zyp[m]>
the first is the Instance() statement, that creates a reference to an external module
<zyp[m]>
and the other is the platform.add_file() that tells the toolchain to include the external verilog file in the build
<zyp[m]>
you can't do the latter without a platform, because without a platform, you don't have a toolchain
<zyp[m]>
if you don't have a platform because you'll be exporting this as another verilog module to include in a larger build, then you simply leave out that part, and then it's on you to ensure that the other verilog file also gets included in the final build
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<Guest96>
Is it possible to add external instance (verilog) without using platform?