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<maikmerten[m]>
not being very familiar with Python, just learning Amaranth - it's still fun to tinker around! Here's a 32-bit RISC-V ALU I cobbled together: https://paste.mozilla.org/XYYykbMy (around ~480 iCE40 cells)
<cr1901>
Looks good to me. One trick you can do to save space is implement signed LT in terms of LTU by inverting the top bit of both inputs to the LTU unit when treating the inputs as signed.
<cr1901>
But measure whether it saves space. It does save space in my particular RV impl, but I've seen it be a net negative.
<maikmerten[m]>
I think I already have an equivalent-ish approach for lt and ltu
<maikmerten[m]>
(basically, lt and ltu are derived from a 33-bit subtraction result, with bit 33 being the "underflow" bit)
<cr1901>
line 87, is xor[31] equivalent to sub[31]?
<cr1901>
Oh wait, nevermind
<cr1901>
I see what you're doing now
<maikmerten[m]>
that's good, because I just cargo-culted that approach from some blog post I read like ~8 years ago ;-)
<maikmerten[m]>
hmm... somewhat surprised my line 129 works: "ack = (~shift) | (shift & shift_finished)". I assumed the correct way would be to "ack = Signal(1)", then do a "comb += ack.eq(...)"
<maikmerten[m]>
(actually, not that surprising thinking about it, given that the expression will also generate a signal)
<maikmerten[m]>
(and it means I can compactify the code here and there)
<jfng[m]>
this paper describes the ALU of NIOS 2, with resource-saving techniques specific to fpga
<jfng[m]>
iirc, the ALU of Boneless also uses similar ideas
<maikmerten[m]>
oh, interesting paper, thanks for sharing!
<maikmerten[m]>
actually, given I already compute "xor = self.I_op1 ^ self.I_op2", I can also replace the "self.I_op1 == self.I_op2" with "~xor.any()", I guess
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<whitequark[cis]>
<maikmerten[m]> "not being very familiar with..." <- the only thing that i really find objectionable is `comb = m.d.comb`
<whitequark[cis]>
`m.<anything>` should be viewed as syntax, like `if` or `else`
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<ldcd[m]>
Would an AXI adition to amaranth-soc be an RFC or just a PR?
<ldcd[m]>
And would it be expected to have feature parity with wishbone (IE Decoder+Arbiter+SRAM?) or would an interface definition and CSR bridge be acceptable as a starting point?
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<tpw_rules>
ldcd[m]: fwiw i have rather janky interface defs and CSR bridges. i need to update them to streams. they're also designed for the weird AXI3/4 hybrid in Cyclone V
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<jfng[m]>
<ldcd[m]> "Would an AXI adition to amaranth..." <- it would need to go through an RFC
<jfng[m]>
<ldcd[m]> "And would it be expected to have..." <- sram and a csr bridge could be done later, i think
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<vegard_e[m]>
you might want to head over to the matrix channel -- people are responding to you there but the bridge is currently only working in one direction so the replies are not getting here
<ldcd[m]>
Right
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<zyp[m]>
I would argue just the interface/signature alone is probably a large enough scope for a RFC
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<AledCuda[m]>
Ok, CSR bridge is my primary use case so I'm planning on doing that anyways, and decoder turned out to not be quite as much of a pain as I thought, arbiter shouldn't be too bad
<AledCuda[m]>
Should I open one RFC for Interface+Signature+Decoder+Arbiter (ie an AXI directory), and one for CSR Bridge and SRAM, or would one RFC for both be acceptable
<AledCuda[m]>
or split Interface+Signature and Decoder+Arbiter
<jfng[m]>
<zyp[m]> "I would argue just the interface..." <- agreed
<zyp[m]>
if the components follow the design of the wishbone equivalents, with the main difference being that they have a different kind of bus attribute, I'm not sure they really need their own RFCs
<AledCuda[m]>
They do
<AledCuda[m]>
Well thats what I'm attempting
<AledCuda[m]>
But I'm happy to open an RFC if it means more eyes in review
<jfng[m]>
for arbiter and decoder, it will probably be easier to directly review the implementation
<AledCuda[m]>
Ok
<AledCuda[m]>
I've seen mention of meetings a few times, do those still occur and are they open?
<jfng[m]>
we only do soc meetings when there are items on the agenda
<jfng[m]>
which are mostly RFCs, but also PRs if needed
<AledCuda[m]>
ok
<AledCuda[m]>
I'll try and open a draft PR with an implementation of each of the discussed parts in separate commits this weekend and then proceed however you see fit
<jfng[m]>
implementation PRs probably won't be reviewed before an RFC for AXI interfaces is accepted
<AledCuda[m]>
Ok, sounds good
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<tpw_rules[m]>
test, the bridge seems to kinda be working okay?
<tpw_rules>
i can see myself both ways
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<Wanda[cis]>
oh hey, nice
<tpw_rules>
hi Wanda[cis] i see you on both irc and matrix
<tpw_rules>
actually maybe it was meant the discord bridge
<Wanda[cis]>
yeah it's the discord bridge that was (and is) broken
<Wanda[cis]>
so no news here
<tpw_rules[m]>
ah, sorry
<tpw_rules[m]>
would definitely be interested to see and help review an interface prototype if you want to do that before the RFC
<tpw_rules>
AledCuda[m]: ^
<AledCuda[m]>
Alright, I'll give you a ping when I push that