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<cr1901>
Finally wrote all the docs for my amaranth simulator wrapper that works with v0.5. This in principle means that I can release it on PyPI right now/tonight! In practice, probably not going to happen due to my executive dysfunction (esp since the Cohost news...)
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<cr1901>
s/wrapper/pytest fixtures/ ... just things that make it less code to parametrize amaranth sims in pytest
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<mabl[m]>
Ah i also have some infrastructure to export signal traces etc. Unfortunately, I have not yet figured out why failing assertions don't give proper failure texts and back trace...
<mabl[m]>
Maybe a pytest thingy
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<trappedinpajamas>
hmm, I'm trying to connect a memory read port to another module with an `Out(Readport.Signature())` , but `wiring.connect()` complains with `TypeError: The initial argument must be a module, not <amaranth.lib.memory.ReadPort object at 0x7bc82d5beea0>`. I assume this is an error of my understanding, since AIUI readport meets the requirements for `Instance` and therefore can be used with `connect()`
<trappedinpajamas>
* an `Out(Readport.Signature(...))` ,
<whitequark[m]>
use wiring.connect(m, read_port, other_port)
<whitequark[m]>
not wiring.connect(read_port, other_port)
<whitequark[m]>
by "a module" it means "a `Module` object" (it's unambiguous but I suppose a little confusing)
<whitequark[m]>
we discussed ctx.changed() and expressions and decided it adds too much complexity to the simulator, but I think there is special handling for edge on 1-bit-wide sig[index] that could be extended to changed
<vegard_e[m]>
in theory, is there anything that prevents a wrapper from introspecting the expression and adding triggers on each separate signal?
<whitequark[m]>
we could reword that message to include my clarification in it
<vegard_e[m]>
it'll be glitchy, but combinatorics necessarily is
<trappedinpajamas>
ah, i totally missed that, makes sense.
<whitequark[m]>
nope
<whitequark[m]>
if you file an issue we could improve the error message