08:10 <_whitenotifier-3> [amaranth] jeanthom commented on pull request #1501: vendor._gowin: fix clock name quotes for Gowin IDE - https://github.com/amaranth-lang/amaranth/pull/1501#issuecomment-2325870472

08:29 <_whitenotifier-3> [amaranth] whitequark commented on pull request #1501: vendor._gowin: fix clock name quotes for Gowin IDE - https://github.com/amaranth-lang/amaranth/pull/1501#issuecomment-2325909805

08:29 <_whitenotifier-3> [amaranth] whitequark commented on pull request #1501: vendor._gowin: fix clock name quotes for Gowin IDE - https://github.com/amaranth-lang/amaranth/pull/1501#issuecomment-2325910793

10:30 <_whitenotifier-3> [amaranth] whitequark commented on pull request #1501: vendor._gowin: fix clock name quotes for Gowin IDE - https://github.com/amaranth-lang/amaranth/pull/1501#issuecomment-2326170183

10:31 <_whitenotifier-3> [amaranth] whitequark reviewed pull request #1501 commit - https://github.com/amaranth-lang/amaranth/pull/1501#discussion_r1741825829

10:42 <_whitenotifier-3> [yosys] whitequark closed issue #37: Stack overflow on moderately deep ternary expression - https://github.com/YoWASP/yosys/issues/37

11:13 <_whitenotifier-3> [yosys] whitequark created branch develop-0.45 - https://github.com/YoWASP/yosys

11:25 <_whitenotifier-3> [yosys] whitequark created branch release-0.45 - https://github.com/YoWASP/yosys

13:29 <_whitenotifier-3> [amaranth] jeanthom reviewed pull request #1501 commit - https://github.com/amaranth-lang/amaranth/pull/1501#discussion_r1742067957

13:32 <_whitenotifier-3> [amaranth] whitequark reviewed pull request #1501 commit - https://github.com/amaranth-lang/amaranth/pull/1501#discussion_r1742072735

13:45 <jorolf> Hey! I'm currently trying to use Amaranth in an existing (VHDL) design. However I've run into a problem with signature port names. The default "namespace" separator is a double underscore, right? Because afaic VHDL doesn't allow double underscores in identifiers which means I can't simply integrate the generated component into my project?

13:45 <_whitenotifier-3> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1501-92439018a4d1f2ad281bc07984e1128ca15b979b - https://github.com/amaranth-lang/amaranth

13:46 <jorolf> So for example if I have a bus with a data port, the generated identifier would be "bus__data"

13:48 <whitequark[cis]> VHDL doesn't?

13:48 <whitequark[cis]> that is news to me; I would have probably strongly considered a different separator if I knew that was the case

13:48 <whitequark[cis]> can you escape an identifier somehow?

13:49 <jorolf> I'm not sure

13:49 <Wanda[cis]> have you tried \bus__data\ ?

13:50 <jorolf> Hmm, not yet

13:51 <Wanda[cis]> but... yeah, VHDL only allows underscores surrounded by digits/letters in basic identifiers

13:51 <Wanda[cis]> (leading/trailing underscores aren't allowed either)

13:51 <jorolf> I've tried to import the component in a Vivado Blockdesign

13:51 <Wanda[cis]> as for "escaping" uhhh

13:52 <jorolf> Which tried to generate a vhdl wrapper that didn't compile because of that problem

13:52 <Wanda[cis]> there's no escapes in basic identifiers; you can, however, use extended identifiers instead which are written between two backslashes

13:52 <Wanda[cis]> they are kinda batshit.

13:53 <Wanda[cis]> they are considered distinct from every basic identifier, and are case-sensitive (as opposed to case-insensitive basic identifiers)

13:53 <_whitenotifier-3> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth/compare/92439018a4d1...0f274291e7e3

13:53 <_whitenotifier-3> [amaranth-lang/amaranth] Jean THOMAS 0f27429 - vendor._gowin: fix clock name quotes for Gowin IDE

13:53 <_whitenotifier-3> [amaranth] whitequark closed pull request #1501: vendor._gowin: fix clock name quotes for Gowin IDE - https://github.com/amaranth-lang/amaranth/pull/1501

13:53 <_whitenotifier-3> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-1501-92439018a4d1f2ad281bc07984e1128ca15b979b - https://github.com/amaranth-lang/amaranth

13:53 <Wanda[cis]> I have honestly no idea how it works for verilog-vhdl interop

13:54 <_whitenotifier-3> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-32/±35] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/81845035a27d...64e1d3caadc4

13:54 <_whitenotifier-3> [amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 64e1d3c - Deploying to main from @ amaranth-lang/amaranth@0f274291e7e3909a2e3f3783fdecd2c5fd565841 🚀

14:03 <jorolf> So a quick google search says that it might work with extended identifiers

14:04 <jorolf> But our project is a Vivado Block Design which auto generates wrapper code around the verilog code

14:05 <Wanda[cis]> ... ah yeah, that's a problem

14:05 <jorolf> Which (apparently) is not smart enough to use extended identifiers in that case

14:11 <jorolf> Is there a way to change the generated names? e.g. by removing the prefix or manually setting the names?

16:29 <mabl[m]> You can rename the port, by attaching a specific porty to the signal

16:30 <mabl[m]> Though I,m not sure that renames the wrapper name. I am using autogenerated verilog wrappers

16:32 <mabl[m]> I'm currently traveling. Will post an example tomorrow.

16:32 <mabl[m]> https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/General-Usage

16:32 <mabl[m]> That, at least, allows renaming the ugly port names on the block diagram

23:51 <le-million[m]> is there a way to convert designs written in amaranth to verilog?