01:57 <cr1901> I added a pipelined BCD converter... latency 4, throughput 1. With hard IP or PipelinedMul, this is a building block for a decimal multiplier on FPGA with throughput of 1: https://github.com/cr1901/smolarith/blob/next/src/smolarith/base10.py#L394-L464

01:59 <cr1901> Unfortunately, I have a few problems generalizing it beyond 6 digits (the paper I took it from goes up to 10 digits/34 bits), and don't feel like tackling those right now. So I think I'll take a break.

02:04 <cr1901> Ya know how like some software libraries will _automatically_ switch between different "strategies" to implement an algorithm depending on the size of the input? Is there precedence for this in Amaranth? Is it even a good idea without giving the user an option to override (which I'm not sure what such an option should look like)?

02:07 <whitequark[cis]> lib.io basically does that

02:08 <whitequark[cis]> but I don't understand why this is needed for this particular problem

02:13 <cr1901> Naive BCD conversion is N^2 LUT usage (purely combinational), and a pipelined alternate algorithm starts giving better LUT usage (approaches 50% fewer resources) after about 15 bits.

02:14 <whitequark[cis]> is the area or the delay the limiting factor?

02:22 <cr1901> It's delay; for a 10-bit delay, e.g. the 3rd bcd digit depends on 8 shift-add-3 units in series

02:22 <cr1901> https://en.wikipedia.org/wiki/Double_dabble#/media/File:Bin2BCD-DoubleDabble2.svg example for 18-bit

02:38 <cr1901> I ran nextpnr-ice40 without pcfs for the purely combinational BCD converters: 10 bits- 20ns, 20 bits- 46.0ns, 30 bits- 75.5ns, 40 bits- 107.5ns, 4 bits (smallest)- 4.2ns

02:38 <cr1901> (No out-of-context mode for ice40 AFAIK, this is the best I can do)

02:40 <whitequark[cis]> put registers before/after

02:49 <cr1901> 4: 305.90 MHz 10: 55.20 MHz 20: 24.70 MHz 30: 14.30 MHz

02:49 <cr1901> Should I even try 40?

02:50 <cr1901> Actually, even 10 is really bad, compared to the paper, so guess I should fix that first

02:51 <cr1901> (Paper got 200MHz on some old Virtex for 20 digits, with suitably pipelined classic shift-add-3 BCD converter)

02:52 <cr1901> And 40: FAIL at 12.00 MHz (10.62 MHz)