<cr1901>
(Also, I think I might've found a vcd bug, but I'm 100% sure. I'll look into it tomorrow.)
<cr1901>
Actually, I can just ask for tomorrow: If generating a sim with VCD, is it normal for pysim to truncate the last half clock tick if the simulation ended due to assertion failure?
<whitequark[cis]>
yeah
<cr1901>
Is there a way for me to force the sim to generate that last half clock tick on assertion failure? Because if a value changed on the same sim time as an assertion failure, gtkwave doesn't really render that well.
<whitequark[cis]>
there isn't
<whitequark[cis]>
it's a gtkwave issue i think
<whitequark[cis]>
so i would recommend reporting it against gtkwave
<cr1901>
You know as damn well as I do that that's not going to do anything
<whitequark[cis]>
at this point i consider vcd a legacy waveform database format so i'm not super interested in improving the experience with using it
<cr1901>
>it's a gtkwave issue i think <-- surfer just plain doesn't generate the transition (or the half tick) at any zoom
<whitequark[cis]>
so i would recommend reporting it against surfer
<cr1901>
Anyways maybe I'll add a pytest hook to open up failing vcds and pad their end time as a workaround
<whitequark[cis]>
yep, works
<cr1901>
Just uhhh... gotta remember how to read and write VCD files LOL (I know there's pyvcd. I'm just too tired to do this tonight)
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<vipqualitypost0[>
i use surfer but i didn't know there was a better format, what should I be exporting my sims as?
<vipqualitypost0[>
(as in still using vcd)
<cr1901>
fst maybe if there's support
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