whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · play https://amaranth-lang.org/play/ · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<cr1901> In smolarith: DeprecationWarning: `a.implies(b)` is deprecated, u
<cr1901> se `~a | b` instead. Looks like I was trying to be cute: https://github.com/cr1901/smolarith/blob/main/src/smolarith/mul.py#L432
<cr1901> It's not even a good use of implies lol
<whitequark[cis]> thank you, this convinces me deprecating it was the right call
<Wanda[cis]> me too
<cr1901> Finally updated the sims for RFC 27 (correctly). That was... not fun. It's gonna take me a while to get used to the new sim behavior now that I've had the experience of fixing tests: https://github.com/cr1901/smolarith/commit/33ed994d2f15aaf9f56f87aae8d9e34df96a2780
<cr1901> (Also, I think I might've found a vcd bug, but I'm 100% sure. I'll look into it tomorrow.)
<cr1901> Actually, I can just ask for tomorrow: If generating a sim with VCD, is it normal for pysim to truncate the last half clock tick if the simulation ended due to assertion failure?
<whitequark[cis]> yeah
<cr1901> Is there a way for me to force the sim to generate that last half clock tick on assertion failure? Because if a value changed on the same sim time as an assertion failure, gtkwave doesn't really render that well.
<whitequark[cis]> there isn't
<whitequark[cis]> it's a gtkwave issue i think
<whitequark[cis]> so i would recommend reporting it against gtkwave
<cr1901> You know as damn well as I do that that's not going to do anything
<whitequark[cis]> at this point i consider vcd a legacy waveform database format so i'm not super interested in improving the experience with using it
<cr1901> >it's a gtkwave issue i think <-- surfer just plain doesn't generate the transition (or the half tick) at any zoom
<whitequark[cis]> so i would recommend reporting it against surfer
<cr1901> Anyways maybe I'll add a pytest hook to open up failing vcds and pad their end time as a workaround
<whitequark[cis]> yep, works
<cr1901> Just uhhh... gotta remember how to read and write VCD files LOL (I know there's pyvcd. I'm just too tired to do this tonight)
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<vipqualitypost0[> i use surfer but i didn't know there was a better format, what should I be exporting my sims as?
<vipqualitypost0[> (as in still using vcd)
<cr1901> fst maybe if there's support
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<_whitenotifier-5> [rfcs] lekcyjna123 reviewed pull request #66 commit - https://github.com/amaranth-lang/rfcs/pull/66#discussion_r1569197288
<_whitenotifier-5> [rfcs] lekcyjna123 reviewed pull request #66 commit - https://github.com/amaranth-lang/rfcs/pull/66#discussion_r1569193330
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<cr1901> http://gopher.wdj-consulting.com:70/paste/23ffbcd7-37b1-453c-ba36-617489b79f28.txt This fixes the VCD truncation I'm seeing, have no idea if it's correct in general, but at least I can monkeypatch to fix it
<cr1901> (ts != PySimEngine.now if an assertion failure interrupts it)
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