<nates93[m]>
Re: convincing others to use Amaranth: how do we prove that amaranth compiled designs are 1. efficient (in terms of area usage) and 2. correct? I understand Clifford/Yosys used VlogHammer to compare synthesis tool results and simulation results btwn simulators. Is there a similar method for Amaranth besides just running very complex designs (e.g. a processor) and verifying correctness (and size, power, etc.) via software?
<nates93[m]>
Have a small slide deck that may possibly make it here
<tpw_rules>
amaranth is pretty 1:1 to verilog, what do you need to compare?
<Darius>
Verilog minus a lot of the footguns anyway
<tpw_rules>
well yeah it's a one way thing. but i think there's not really any efficiency impact. there is a very small one in avoiding footguns
<tpw_rules>
as for correct i'm not sure
<jn>
formal verification (using symbiyosys) comes to mind for the correctness question, but i don't know enough about it to go into detail
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[amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1265-2cf9bbf306864a1e1d3358020a3c71f3a09b236f - https://github.com/amaranth-lang/amaranth
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[amaranth-lang/amaranth-lang.github.io] whitequark e18a1e2 - Deploying to main from @ amaranth-lang/rfcs@27ecea8cdc46c938ee1a8a5917e3a9cac8242939 🚀
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[amaranth-lang/amaranth-lang.github.io] whitequark c07868d - Deploying to main from @ amaranth-lang/playground@636c2e4d3ba2453badbe6fc8b4e13fe9c6815436 🚀
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<ldcd[m]>
I'm reimplementing several of my works bugged DSP modules in amaranth I've been doing this with ad-hoc fixed point. If vegard_e (@_discord_157944445168254976:catircservices.org) has other parts of the language they would rather work on I can contribute a draft implementation of RFC#41 as part of my job. I can also likely contribute an FFT generator to amaranth.lib once the stream RFC and RFC#41 get merged if there is interest.
<whitequark[cis]>
ldcd: in any case, getting more production experience with the fixed point module will be extremely valuable and (especially after the 0.5 release) I'm very interested in working with you on it
<whitequark[cis]>
an FFT generator is something that might be better prototyped out of the standard library, potentially; but since I don't really understand the domain involved I can't confidently say that it should or shouldn't be
<ldcd[m]>
zyp: Sorry I missed that thank you for linking it
<ldcd[m]>
in that case I will prototype an FFT and a few FIRs with the draft implementation
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<nates93[m]>
Is it true CXXRTL is basically an iverilog (able to handle delays, etc.) but with speeds closer to Verilator?
<whitequark[cis]>
I feel like that particular statement is too likely to mislead a reader into thinking that CXXRTL is something that it isn't
<whitequark[cis]>
for one, CXXRTL doesn't handle 4-valued logic at all, and never will (3-valued perhaps)
<whitequark[cis]>
* (3-valued perhaps, though it's probably going to be mostly handled by a pass above CXXRTL)
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<galibert[m]>
4-value, that’s 01zx?
<whitequark[cis]>
yes
<galibert[m]>
X maybe Z never right?
<whitequark[cis]>
yes. I mean Yosys has a pass that lowers X to a [01] side-signal, and it wouldn't be too hard to associate both with each other somehow so that x can be shown for presentation
<whitequark[cis]>
the pass is xprop
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[amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1274-f21d3d0c6a34bce5d05290f4f62796f3b0b7671f - https://github.com/amaranth-lang/amaranth
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