whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · play https://amaranth-lang.org/play/ · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<cr1901> Did more monkeypatching- no, my linked code is definitely not a correct solution in general- I didn't guard against adding multiple layers of wrapper calls LOL)
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<whitequark[cis]> you could probably just append #1000 to the VCD file as text
<_whitenotifier-6> [rfcs] whitequark reviewed pull request #66 commit - https://github.com/amaranth-lang/rfcs/pull/66#discussion_r1569851019
<_whitenotifier-6> [rfcs] whitequark reviewed pull request #66 commit - https://github.com/amaranth-lang/rfcs/pull/66#discussion_r1569851748
<cr1901> whitequark[cis]: Maybe, but I'm kinda nerdsniped looking at the simulator internals anyway right now. There are worse uses of my time
<whitequark[cis]> it has the advantage of not breaking when we improve the simulator (though, i don't recall if those delays are absolute--absolute ones would be more annoying)
<cr1901> they're absolute
<cr1901> (emphasis AFAICT)
<whitequark[cis]> right. i guess a regex then or something >_>
<cr1901> Or iterate over the file until the last clock entry w/ pyvcd, save it, then reopen the file for appending
<cr1901> and add "#last_timestamp + 1000" to the end
<whitequark[cis]> also works
<cr1901> My current understanding is "when a testbench is finished, the clock process with the nearest edge will be schedule, and that causes the linked line to fire and extend the VCD until the next (active or inactive!) clock edge: https://github.com/amaranth-lang/amaranth/blob/main/amaranth/sim/pysim.py#L622
<cr1901> When a testbench asserts, the clock process is never schedule (which makes sense), and the linked line will fire without having extended the VCD time
<cr1901> Or "something like that"
<cr1901> https://github.com/amaranth-lang/amaranth/blob/main/amaranth/sim/pysim.py#L618-L621 What are your thoughts about adding an except: block with "self._timeline.now += 1000" here?
<cr1901> The sim already died at this point, and the finally will run immediately after, so it's fine that we lie about the actual timeline? :D
<whitequark[cis]> cr1901: no magic constants
<whitequark[cis]> cr1901: not fine with it
<whitequark[cis]> gtkwave should fix the presentation
<whitequark[cis]> by showing a bunch of dotted lines extending the last state or whateber
<whitequark[cis]> s/whateber/whatever/
<cr1901> (Note to self: 1000 is tool small)
<cr1901> too* small
<cr1901> https://github.com/gtkwave/gtkwave/issues/230#issuecomment-2062918577 gtkwave has an open issue, I made a comment
<cr1901> >The way I've dealt with this is to click on the signal then arrow right to the very last signal transition. <-- this also works as a workaround
<cr1901> "Now I will have less distraction"
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<whitequark[cis]> empirically, building a 10/100 MAC essentially from scratch, including a bunch of stream infrastructure, with Amaranth and Glasgow takes less than four days
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<bl0x[m]> Sweet!
<whitequark[cis]> adamgreig: you're right, a packet queue is very useful
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<adamgreig[m]> Yea, I use them all over
<adamgreig[m]> <whitequark[cis]> "empirically, building a 10/100..." <- Now do an IP stack!
<adamgreig[m]> I found rgmii so so much easier to do the mac for than rmii
<adamgreig[m]> Never tried rgmii in 10 or 100 mode though
<whitequark[cis]> this is exactly why I bought an RGMII PHY
<whitequark[cis]> it works basically exactly the same as in 1000 mode, but you discard DIN1 and use only DIN0
<adamgreig[m]> Sure sounds easier than rmii
<adamgreig[m]> The phys are bigger and more annoying and a little less well stocked in my experience though
<whitequark[cis]> I got an RTL8211
<adamgreig[m]> Think that's what I used too. Did I see you making a delay line? Was that for the rgmii?
<_whitenotifier-5> [amaranth] wanda-phi opened pull request #1338: vendor._lattice: merge ECP5 and MachXO[23] into one platform. - https://github.com/amaranth-lang/amaranth/pull/1338
<whitequark[cis]> you can get bare parts for like a $1
<whitequark[cis]> adamgreig[m]: yes. the PHY can do this too, but I didn't feel like desoldering a resistor on the board
<whitequark[cis]> so now I have a general solution :D
<adamgreig[m]> Ah fair enough
<adamgreig[m]> I definitely just had the phy do it :p
<adamgreig[m]> But I was making the board from scratch anyway so wasn't a problem to strap it
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<whitequark[cis]> the default strap configuration actually works just fine
<whitequark[cis]> but for some reason on this board RX was configured without delay
<whitequark[cis]> I could have removed a single SMT resistor but I was feeling tired that day and didn't want to get my soldering iron
<whitequark[cis]> so I figured out how to do IODELAY on ice40 and qualified it somewhat
<_whitenotifier-5> [amaranth] codecov[bot] commented on pull request #1338: vendor._lattice: merge ECP5 and MachXO[23] into one platform. - https://github.com/amaranth-lang/amaranth/pull/1338#issuecomment-2064177294
<_whitenotifier-5> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1338-a7a7d3209948b0f48f9ff275140850cdae408983 - https://github.com/amaranth-lang/amaranth
<_whitenotifier-6> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to main [+3/-5/±2] https://github.com/amaranth-lang/amaranth/compare/a7a7d3209948...09045a2724ce
<_whitenotifier-5> [amaranth-lang/amaranth] wanda-phi 09045a2 - vendor._lattice: merge ECP5 and MachXO[23] into one platform.
<_whitenotifier-6> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-1338-a7a7d3209948b0f48f9ff275140850cdae408983 - https://github.com/amaranth-lang/amaranth
<_whitenotifier-5> [amaranth] whitequark closed pull request #1338: vendor._lattice: merge ECP5 and MachXO[23] into one platform. - https://github.com/amaranth-lang/amaranth/pull/1338
<_whitenotifier-5> [amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 36c3b9e - Deploying to main from @ amaranth-lang/amaranth@09045a2724cee50f4d285066e8018d3a882d1785 🚀
<_whitenotifier-6> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+8/-12/±36] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/f3542d991a96...36c3b9e92eec
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<eigenform> is there something special i need to do in order to get an editable local package from pdm?
<eigenform> it seems like pdm_build.py:9 is upset because my SCMVersion is '0.0'?
<cr1901> Are you on Windows/MSYS2 by any chance?
<eigenform> this is on archlinux. pdm-backend doing something funky
<eigenform> ah - i needed to grab the tags from amaranth upstream :^) oops
<cr1901> http://gopher.wdj-consulting.com:70/paste/b47b0a7b-5c96-4da2-81dc-a488fa34e4a0.txt Useful 4-line snippet that took me surprisingly long to get right (decorator for amaranth testbenches that take arguments): http://gopher.wdj-consulting.com:70/paste/b47b0a7b-5c96-4da2-81dc-a488fa34e4a0.txt
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<whitequark[cis]> <eigenform> "it seems like pdm_build.py:9..." <- I think you need to check out repo tags, potentially
<eigenform> yeah, i forked and forgot to grab them ^^ thanks
<_whitenotifier-6> [amaranth] eigenform opened issue #1339: Can't emit Verilog/RTLIL with Signature array members - https://github.com/amaranth-lang/amaranth/issues/1339
<_whitenotifier-6> [amaranth] whitequark commented on issue #1339: Can't emit Verilog/RTLIL with Signature array members - https://github.com/amaranth-lang/amaranth/issues/1339#issuecomment-2065453889
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<_whitenotifier-6> [amaranth] eigenform opened pull request #1340: back.verilog, back.rtlil: map path elements to str - https://github.com/amaranth-lang/amaranth/pull/1340
<_whitenotifier-5> [amaranth] whitequark reviewed pull request #1340 commit - https://github.com/amaranth-lang/amaranth/pull/1340#discussion_r1571494871
<_whitenotifier-5> [amaranth] codecov[bot] commented on pull request #1340: back.verilog, back.rtlil: map path elements to str - https://github.com/amaranth-lang/amaranth/pull/1340#issuecomment-2065468395
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