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<whitequark[cis]>
adamgreig: I've updated the CRC module to be in line with the documentation we have elsewhere in Amaranth, and fairly heavily edited the text for clarity and conciseness
<whitequark[cis]>
(in particular I've excised sentences of the form "uses :class:X, refer to documentation of X for details", everyone knows how hyperlinks work)
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<adamgreig[m]>
<whitequark[cis]> "adamgreig: I've updated the..." <- thanks, lgtm. "Compute a CRC in hardware using the predefined CRC16-CCITT algorithm and the data word width of 8 bits" should probably be an indefinite article on data word width?
<adamgreig[m]>
why is self.crc_width, self.initial_value etc now converted using index instead of int? I thought index was for things that will be used as an index, but this is being used as an actual integer
<adamgreig[m]>
* why is self.crc_width, self.initial_value etc now converted using __index__ instead of int? I thought index was for things that will be used as an index, but this is being used as an actual integer
<adamgreig[m]>
(I appreciate it means that a string representation of an integer won't get converted which is probably a more useful behaviour though)
<adamgreig[m]>
in "A trailing CRC data word is also known as a codeword", the codeword is the combination of all the data and its trailing CRC, not just the trailing CRC alone
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<sys64738_2574[m]>
hi, is there any way to specify the frequency of the clock of a user-defined clock domain that's 100% internal to the fpga fabric?
<sys64738_2574[m]>
i currently have this design for xilinx 7-series, using an MMCM primitive to generate a lower-frequency clock for some logic. vivado seems to infer the frequency of the clock by itself and uses it to check whether the low-speed design meets the timing constraints. though, is there any way to make this explicit? id imagine that porting it to a different FPGA (using a different primitive & toolchain), or even a vivado update,
<sys64738_2574[m]>
would make this bit of magic clock constraint discovery break, so id like to have some safeguards here by specifying constraints manually, without having to create a fake pin etc.
<whitequark[cis]>
<adamgreig[m]> "(I appreciate it means that a..." <- it is for this reason
<whitequark[cis]>
<adamgreig[m]> "in "A trailing CRC data word..." <- honestly I've never heard this terminology before so I was rather confused as to what is actually meant (since you've never defined it)
<adamgreig[m]>
ah, it's a term of art for coding and CRCs
<adamgreig[m]>
we could not mention it at all in the docs, but if we do it must refer to the "data + crc" combination
<whitequark[cis]>
sys64738_2574: there's nothing magic about it and e.g. nextpnr does it too; the toolchain knows the MMCM settings (they're unambiguous) so it knows exactly what the clock constraint should be, and how to propagate it through elements like BUFGCEs and such
<adamgreig[m]>
wikipedia offers:
<adamgreig[m]>
A CRC-enabled device calculates a short, fixed-length binary sequence, known as the check value or CRC, for each block of data to be sent or stored and appends it to the data, forming a codeword.
<adamgreig[m]>
When a codeword is received or read, the device either compares its check value with one freshly calculated from the data block, or equivalently, performs a CRC on the whole codeword and compares the resulting check value with an expected residue constant.
<whitequark[cis]>
i... see
<whitequark[cis]>
that is incredibly confusing actually
<adamgreig[m]>
(for the same reason I used "residue" instead of "residual value")
<whitequark[cis]>
since you have a "data word" and "codeword" and the latter is never defined and confusable with the former
<adamgreig[m]>
it's because CRCs are linear codes, a field of study with a set of specific well-defined terms including codeword
<adamgreig[m]>
and then I guess they leaked :P
<adamgreig[m]>
practitioners finding uses for theory causing trouble yet again
<adamgreig[m]>
(this is also why hamming distances are relevant to CRCs and their ability to detect errors)
<sys64738_2574[m]>
ah alright, thanks
<tpw_rules>
i'm with wq here
<whitequark[cis]>
there are very few cases where you need a clock constraint in a situation like that; chiefly if you use a BUFGMUX in a complex topology and the default behavior (applying both constraints to all clock pins) results in impossible timing arcs
<gruetzkopf>
i have read codeword in CRC context (well, germanised "Codewort" precisely in one document by siemens - with the same meaning
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