<jjsuperpower>
I have been learning how to use the FSM library in Amaranth and noticed something odd.
<jjsuperpower>
Let's say we have a FSM with two states, state1 and state2, and one output (reset = 0). In state one, the output is set to 1 in the combinational domain.
<jjsuperpower>
In state two, the output is not modified at all. The result is the output will be high (1) in state one, but not in state two. However, if we use the sequential domain in state one the output will be high in both states.
<jjsuperpower>
From my understanding this makes creating mealy machines somewhat annoying as a combinational signal needs to be defined in every state.
<jjsuperpower>
My question is: Is this behavior intentional or am I doing something wrong? - Thanks
<whitequark>
this is intentional
<whitequark>
the current FSM sub-language is known to be limited, could you please create an issue with the description of your scenario so that it can be used as an input in a future redesign?
<adamgreig[m]>
jjsuperpower: how else could it work? would you want it to clear the output register in state 2 if you don't explicitly do anything there?