cr1901 changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://libera.irclog.whitequark.org/~h~yamahasynths
<cr1901>
I've decided to rent out PA-RISC server space from one of our resident catgirls for the time being (when the time is right)
<cr1901>
(No, SCSI is not selling server space. This is a catgirl of the non-shoebox-sized, walks-on-two-legs, much-more-than-100-vocalizations kind)
<andlabs>
lol
<andlabs>
well an SGI machine isn't going to help with PA-RISC anyway so
<andlabs>
also is it hppa32 or 64?
<cr1901>
true
<andlabs>
I'm still looking at that one hppa64 tower I can import
<andlabs>
(I bought an hppa32 already)
<cr1901>
No idea... either is fine, but 32 preferred
<cr1901>
Mix of both, apparently
<madeline>
are you trying to collect every major architecture ever made
<madeline>
because i tried that
<madeline>
and that's how i ended up with weird shit
<cr1901>
andlabs or me?
<madeline>
andlabs
<cr1901>
In my case, PA-RISC is "I just think it's neat" MargeSimpson.gif. No reason for me to prefer that RISC to any others in the sea of Me-Too RISC. Well, besides the ones I've used :P.
<sorear>
the only slightly shorter list of "architectures designed to replace 68000"
<andlabs>
I mean
<andlabs>
yes
<andlabs>
it activates a part of my brain from when I was really young and just mad e up computers
<cr1901>
Thank you sorear for teaching me the term "Me-Too RISC"
<andlabs>
the risc wars of the 1990s were a thing
<andlabs>
I bought an intel i860 chip for some reason
<sorear>
can't remember anymore where that came from
<qu1j0t3>
andlabs: Because you're going to make an SBC.
<cr1901>
Well, it's apt. Though I think each RISC is precious and unique <3... kinda.
* sorear
thinks a collection of one of every arch would get very heavy with old minicomputers
<cr1901>
and expensive
<tpw_rules>
apropos of nothing i feel like power pc is 68k's true successor
<tpw_rules>
is that just me
<cr1901>
88k?
<tpw_rules>
i mean there is that but like spiritually.
<andlabs>
I found an instnace of the phrase from a 1988 issue of byte
<andlabs>
"I find the Linn Rekursiv an interesting development for several reasons. Its sheer originality offers some relief from the flood of 'me-too' RISC chips which threaten to drown the industry."
<andlabs>
from an article called "Rekursiv: an object- oriented cpu"
<cr1901>
Rekursiv doesn't exist anymore, AFAIK. One of the only hardware samples is at the bottom of a river
<madeline>
i have an 88k machine
<madeline>
i found it locally lol
<cr1901>
Eric Smith/brouhaha on Twitter found the manual via an inter-library loan. I should poke him again and see what came of that
* sorear
vague motion at the dozens of ppc samples on mars
<madeline>
mars/ppc
<tpw_rules>
was 68k ever in space?
<sorear>
SSMEs used it for a while
<cr1901>
68k In Space sounds like a cheesy B-movie title
<andlabs>
aaaa an 88k
<andlabs>
let me guess
<andlabs>
is it data general?
<madeline>
nope
<madeline>
motorola
<andlabs>
even better :O
<madeline>
powerstack :D
<cr1901>
Why would motorola make 88k machines? :P
<andlabs>
I rarely see any obscure shit like 88k on ebay; I saw data general 88k once but that was it
<madeline>
i don't own anything data general, as surprising as that sounds
<andlabs>
steal all of tech tangents's minicomputers
<cr1901>
I don't watch him... I'm sure he's a nice guy, but his videos just don't do it for me
<andlabs>
I still wnat to design my own CPU one day
<andlabs>
I should learn fpga and also kicad
<tpw_rules>
it's decently fun
<cr1901>
/join #nmigen
<tpw_rules>
i did a quasi-cpu in nmigen
<andlabs>
does /cs info not print topics
<cr1901>
still need to learn kicad, but... uhhh... as much as it's improved, yea, I still don't like its project/parts management, sorry :(
<tpw_rules>
what is the problem with it?
<andlabs>
"nMigen is not a "Python-to-FPGA" conventional high level synthesis (HLS) tool. It will not take a Python program as input and generate a hardware implementation of it."
<andlabs>
oh god just imagine
<andlabs>
entire chips that are literally just numpy
<cr1901>
tpw_rules: Is cache.lib still a thing?
<tpw_rules>
probably? i don't remember the details, just not being unhappy
<cr1901>
Well, that's one of the big ones, where cache.lib would interact poorly with parts libraries on my path. Also find it difficult/effort to use a fork of kicad's upstream parts libraries temporarily
<cr1901>
And the 7400 library's power/gnd pin handling.
<cr1901>
(They are implied connections)
<andlabs>
hmm
<andlabs>
looks like lambdaconcept deleted their blog and all their posts and started over
<andlabs>
which is a problem because one of the tutorials for that nmigen thing was one of the deleted posts
<NiGHTS>
GitHub - nmigen/nmigen: A refreshed Python toolbox for building complex digital hardware
<andlabs>
I got to that link from the github page though
<andlabs>
wait
<andlabs>
that's a different repo
<andlabs>
nmigen/nmigen vs m-labs/nmigen
<cr1901>
Yes, see privmsg
<andlabs>
sounds like there's some google search order that needs fixing
<cr1901>
Anyways, I would suggest getting an ice40 dev board like icebreaker and learning nmigen if you're okay w/ Python
<cr1901>
Not sure about the Go offerrings for FPGA dev (nor am I paying attention to them)
<tpw_rules>
i would also suggest this
<andlabs>
I don't know if there would even be any
<andlabs>
skimming those tutorials I have a feeling I do not understand FPGAs as opposed to intuitive understanding of circuits so uhhh maybe some other time
<tpw_rules>
what do you intuitively understand about circuits
<andlabs>
I guess I went in expecting something like "hook up these two fundamental components directly in the sense of one of ben eater's breadboard tutorials" and got confused
<andlabs>
look I've got other stuff right now I might be talking ottal garbage
<andlabs>
sorry
<tpw_rules>
that's okay i was just curious what you had learned before
<cr1901>
nmigen is for designing the DIP ICs you would place on a breadboard, and _then_ connecting them together :)
<andlabs>
oh yeah I just thought that it's just layers of abstraction
<andlabs>
that such an IC can be deconstructed in a similar way
<andlabs>
see also monster6502
<cr1901>
I mean, you could do that with nmigen
<andlabs>
yeah
<andlabs>
I just got confused by the tutorials talking about things that made no sense
<andlabs>
I am probably thinking of things wrong and also not yet in the right mindset to do anything
<qu1j0t3>
it takes a little bit of adjustment, yeah
<qu1j0t3>
depending where you're coming from
<cr1901>
HDL is a "spooky action at a distance" language
<tpw_rules>
why do you say taht?
<cr1901>
Because I don't know a good analogy for "HDL is Functional Reactive Programming, except with wires")
<tpw_rules>
i mean that's what i was going to say
<tpw_rules>
also i think it is valuable to be able to see the circuit in your head
<tpw_rules>
it's not really programming, it's description. like the name says
<andlabs>
brb
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<andlabs>
back
<andlabs>
fair
<andlabs>
for the record my first experience with any of this was watching mist's 6502 talk and then looking up visual6502 / perfect6502 and trying to figure out how toa dapt it to expose signals as go channels and then wondering why it locked up
<andlabs>
I never quit eunderstood that
<andlabs>
the wolfenstein 3d on 32x guy once tried to explain it but
<andlabs>
well it as in how transitors actually worked in that particular netlist sense
<andlabs>
the point being i never *quite* understood hardware :D
<tpw_rules>
fpgas are kind of unrelated to that imo
<cr1901>
You're not going to make an NMOS 6502 on FPGA, if that's your goal (not easily anyway)
<tpw_rules>
like you cannot drop a 6502 netlist in an fpga. the building blocks aren't compatible
<tpw_rules>
i mean you can design a circuit which functions more or less identically to the documented behavior of an nmos 6502
<cr1901>
that's the "not easily" part
<sorear>
need a TRNG for some of the unofficial instructions?
<cr1901>
and someone has done it by analyzing the 6502 netlist
<tpw_rules>
well it's no harder than any other circuit
<tpw_rules>
i think almost all the 6502 undocumented opcodes are predictable actually. so you could do those too
<cr1901>
Idk if it was dropped in to a 80s computer using a 6502 (plus level shifters) tho
<tpw_rules>
you don't need to make it anywhere near that complicated
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<andlabs>
CONFIRMED the problem with my computer constnatly going tinot hibernate is that the battery gets disconnected somehow temporarily; now I have to figure out why
<andlabs>
it just happened now while unplugged and not only would the compute refuse to turn on but the battery level button stops responding. Now I just have to figure out why. If there's a way to override the forced-hibernation behavior while the computer is plugged in that would also be great...
<andlabs>
also just gonna leave this in here in jest
<NiGHTS>
Ashlynn (fake gamer girl comics) sur Twitter : "It has to be said!! 😾😾😾… "
<cr1901>
har de har har :P
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<endrift>
wonder how often three or more people from this channel are in the same building at the same time
<endrift>
it happened on Friday!
<cr1901>
you, madeline, and Foone?
<cr1901>
oh right, SCSI is an honorary idler in this channel, I decided (cc: Foone). She just can't join due to the lack of opposable digits
<sorear>
how many people here do fosdem or ccc?
<sorear>
seems like 3 is easy to hit in that case
<cr1901>
I've met balrog in person once, so that's 2 ppl in the same building
<sorear>
could get quite a few people with "was in the same train station at the same time but unaware of each other's presence" for majorish cities
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<andlabs>
anyway late but no my goal was not to do 6502 in fpga
<andlabs>
but rather to experiment with a particular means of API-izing chip emulation
<andlabs>
" Combinatorial loops do not work well in FPGA logic. Transparent latches are not the only problem. The 6502 contains S-R (set-reset) type latches made from cross-coupled gates; and numerous potential feedback loops in the data path. All circular paths are broken by inserting registers after every node. The minimum FPGA to 6502 clock ratio depends on the number of logic levels through which signals must propagate on each 6502 clock. Some
<andlabs>
registers could possibly be removed; but keeping them eases timing closure. The next state of every node in the chip is a combinatorial function of their previous states and those of external stimuli: "
<andlabs>
that sounds. ... very inconvenient for FPGA
<andlabs>
unless we've figured out ways to do combinatorial loops without actually doing combinatorial loops?
<NiGHTS>
foone sur Twitter : "my assembler uses a different syntax than my disassembler, and the matching disassembler asserts when trying to disassemble the file… https://t.co/izDAHApNj4"
<andlabs>
the true IDA experience™
<furan>
6502 works on FPGA fine, at least kevtris has implemented them several times over, starting from schematic input, now verilog these days
<furan>
combinatorial logic synthesizes just fine, but when you write any combinatorial logic, you have to do it while thinking about the signal propagation delay you are creating
<tpw_rules>
in fairness kevtris is not trying to duplicate the internal architecture. just the functionality
<NiGHTS>
AI except neither Artificial nor Intelligent sur Twitter : "Although you certainly can chain LUTs to get more complex combinatorial logic, normal FPGAs are fundamentally intended to implement synchronous logic. The LUTs may not be glitch-free, which is not a problem when they only feed a DFF and have no combinatorial feedback.… https://t.co/Ym8i3AtsMP"
<cr1901>
One basic unit of FPGAs is the Look Up Table- LUT. LUTs can emulate different types of logic gates- AND, OR, NOT, etc
<cr1901>
An SR latch can be implemented in terms on NAND gates whose outputs feed back into your inputs
<cr1901>
The linked tweet explains a bit why "you can't emulate a latch by using LUTs as NAND gate substitutes"
<andlabs>
ah yes combinatorial vs synchronous logic; that's something I saw in one of the tutorials and don't know anything about yet
<andlabs>
I'll look at this though thanks
<andlabs>
*this thread
<andlabs>
in fact the fact that they are different types of logic is a new concept to me
<qu1j0t3>
andlabs: I think i've recommended it in here before, but Wirth's Digital Circuit Design for Computer Science Students helped _me_ a lot, it's practically a full course from transistor to HDL to CPU
<andlabs>
ok
<qu1j0t3>
has exercises
<tunixman>
It's an excellent resource.
<qu1j0t3>
i mean i don't want to labour the point but he is an outstanding teacher and pedagogical writer
<qu1j0t3>
you kind of get to "okay we're building a whole ass cpu" without even noticing the walk
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<tunixman>
a few transistors here, a few transistors there, pretty soon it adds up to a real ALU.
<NiGHTS>
What is better than a Yamaha FS1r with a HW Controller? - YouTube
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<furan>
< tpw_rules> in fairness kevtris is not trying to duplicate the internal
<furan>
architecture. just the functionality
<furan>
this is absolutely wrong and the difference between what kevtris does and what the mister folks do - all this time he has been trying to duplicate the logic; he looks at the silicon. sometimes he is able to do it, sometimes he can't.
<tpw_rules>
looking at the silicon doesn't mean reimplementing the silicon
<furan>
I don't say that because he looks at the silicon
<furan>
this is dumb bye
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<tpw_rules>
?
<alexisvl>
what just happened
<qu1j0t3>
microdrama
<alexisvl>
i didn't even get a micropopcorn
<tpw_rules>
i guess?
<tpw_rules>
i don't know who furan is
<qu1j0t3>
alexisvl: You did, but you need a microscope to see it
<alexisvl>
oh.
<qu1j0t3>
:)
<qu1j0t3>
tpw_rules: I've read that exchange five times now and at best i get 'violent agreement'
<tpw_rules>
(i know very well who kevtris is though)
<andlabs>
I
<andlabs>
okay
<andlabs>
I'll just not bother looking at the logs I missed for now
<andlabs>
unless someones aid something to me after [17:44:09] <qu1j0t3>you kind of get to "okay we're building a whole ass cpu" without even noticing the walk
<qu1j0t3>
andlabs: nothing relevant was said after that :)
<tpw_rules>
yeah you didn't come back in the middle of anything
<andlabs>
also of course nikalus wirth did this
<andlabs>
still need to set up an oberon system at some point
<andlabs>
if libui on oberon is even feasible
<cr1901>
>tpw_rules: i don't know who furan is
<cr1901>
He created a custom PCI express gfx card and an accompanying Windows driver. He clearly knows his FPGA stuff. That being said
<cr1901>
IIRC, kevtris' NES core runs at 10 times a real 6502 does, so it may very well be indistinguishable at the pin level from an NMOS 6502 for everything besides the clock
<cr1901>
But it is not a drop-in replacement for your dying 2A03 chip on your NES
<cr1901>
(precisely because it's using a 10 times clock... maybe you can generate the 10 times clock from the NES itself. But not on ice40, since the PLL only goes down to 3MHz)
<tpw_rules>
my point is i'm pretty sure it's not implemented by duplicating the transistor layout of the 2a03
<tpw_rules>
i know he's studied the transistors to answer questions of behavior in corner cases
<tpw_rules>
in fact my claim must be true because the real 2a03 does not have a ten phase clock
<tpw_rules>
(also, where did you hear that detail?)
<andlabs>
this is also my problem with FPGA clones
<cr1901>
tpw_rules: I asked him once when he was on Freenode :P
<cr1901>
It _may_ also be on his website about the bringup of his FPGA NES
<tpw_rules>
hm, i've never run into him on freenode
<andlabs>
that we don't really describe timing intricacies and analog weirdness well
<andlabs>
the C64 PLA fiasco should prove that we should be preserving timing intricacies
<cr1901>
He doesn't appear to have made the transition to libera
<andlabs>
I thought kevtris was actually in this channel once but no that was nukleykt
<cr1901>
No, kevtris _was_ also in the channel once
<cr1901>
He left because he had too many channels
<andlabs>
oh boy
<tpw_rules>
?
<andlabs>
too many IRC channels is always fun
<cr1901>
tpw_rules: I asked kevtris. First off, it's 12x or 16x faster, but yes, the core runs with a multiplier. The core itself is stepped using the clock-enable every n cycles.
<cr1901>
What I didn't know is that the 2a03 does a divide of the clock internally. So in principle yes, his core is a drop-in replacement