azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
<agg>
in principle my specan is doing the first OK, it's just a question of how bad its own phase noise is... but i think you could measure jitter directly with either scope or timer, just not sure which will be better
<agg>
well, with the direct period measurements, i get 16ps rms jitter on the xo output, and 74ps rms jitter on the pll with the ecppll suggested settings
<agg>
so maybe this method has something going for it
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<Degi>
Ohhhh
<Degi>
Can I measure jitter in the ECP5? with an 18 ps delay line
<Degi>
At least my frequency measurement with the scope yielded like 1 MHz stddev, which seemed a bit high to me
<Degi>
Like 99.3 MHz with 2.4 MHz deviation, 10 ns +- 260 ps
<tnt>
Does your scope have a hw frequency counter ?
<Degi>
Yeah its kinda shit
<Degi>
And don't you need to do measurements over as few periods as possible?
<Degi>
(My program needs about 1-2 periods (depending on how close its to a sine wave) to get the frequency)
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<agg>
for period jitter you just need to measure a ton of randomly selected periods, for cycle-to-cycle jitter you need to measure two consecutive periods and look at the abs difference between them
<agg>
the scope's frequency counter will probably work out average frequency over a number of periods which would average out cycle to cycle/period jitter so might not be ideal for measuring that
<Degi>
Though measuring the period of a cycle is a bit hard, especially since the noise of the oscilloscope would make it pretty bad if you simply measured the time when it crossed the threshold
<Degi>
(My code uses linear regression for that, where each sample contributes to the period, but this only works well with sinewaves)
<Degi>
(I guess I could use a function which approximates the waveform, though simply combining five sine waves at harmonics doesn't give that good results)
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<agg>
Degi: I'm measuring with a hardware timer that has a single-period mode and 20ps resolution
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<agg>
if you're fitting to multiple cycles, you'll be averaging out cycle-to-cycle variation, and just seeing much longer-scale slow change in frequency?
<Degi>
Hmm, I'm fitting to one or two cycles
<Degi>
Though I guess I could put such a timer directly onto the ECP5, then it doesn't need any external hardware besides a clock source
<agg>
yea, could work! how would you get the resolution you need without running it off the PLL itself?
<agg>
so long as the temperature is stable and you don't care about the actual frequency, only the period to period jitter, it seems like it could work well
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<Degi>
I think it was that one, on my FPGA it had 18 ps between two LUTs
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