azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
<agg>
does anyone happen to know if i'll get in trouble connecting the serdes vcc to gnd on an ecp5? the migration app note says you can wire them to vcc on a non-serdes part to enable migration, but i just want to fit a serdes part and not use the serdes
<agg>
given the suspicion that the serdes is pinned out on all the parts anyway i guess it's probably fine regardless...
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<emeb_mac>
agg: that they're all pinned out seems to be the consensus after some close looks at the parts and data a few years ago.
<emeb_mac>
but I'm not sure if anyone has actually tested that conjecture.
<agg>
if true, presumably no harm will come from tying all the serdes vcc to gnd then, since that's what lattice recommend for the lfe5u in footprints that could have serdes?
<emeb_mac>
seems like a safe assumption.
<emeb_mac>
I suppose you could bring those pins out to a separate plane and tie that to vcc or gnd at test time.
<agg>
I guess ideally I should bring out the serdes too and see if they really exist :P
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