azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<Degi>
The manual says (CLKO<n>_FPHASE/(8*CLKO<n>_DIV)]*360° and [(CLKO<n>_CPHASE – CLKO<n>_DIV)/(CLKO<n>_DIV + 1)]*360° I think adding them together should give the total phase shift of a given output
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<Peanut>
Degi: Thank you, that lead me to the 'dynamic' phase shifting part of the docs. It seems as if 'coarse' and 'fine' are really related to the phase step sizes for the VCO and Divider. But then again, Table 18.7 seems to imply that they are the actual phase offset values.
<Peanut>
I'll have to hook up my oscilloscope tonight and see if that clarifies the issue.
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<Degi>
Table 18 in TN1263?
<Peanut>
No, in TN02200 (sysCLOCK DLL/PLL Design and Usage Guide). Hmm, curiously, TN1263 has the same title, and looks similar. But TN1263 is from November 2015, and the TN02200 is from Januari 2021.
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<Degi>
Oh cool, new datasheets
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<agg>
the changelog says it adds disclaimers, acronyms, removed OSCG features
<agg>
not very exciting alas
<agg>
Peanut: the ecppll binary might have some clues on the loop parameters... i did some playing with the ehxpll a while back to try and use it for clock recovery by tweaking the phase at runtime and got it basically working but I think I ended up just using PHASEDIR and PHASESTEP inputs with CPHASE=12 and FPHASE=1
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<Degi>
Interesting, the old datasheet says "It has an input to dynamically control standby/normal operation." but the input isn't mentioned anywhere else.
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<Peanut>
I've already looked at (the source of) the ecppll binary. It comes up with some numbers that I don't quite agree with :-)
<Peanut>
agg: What in your opinion do CPHASE and FPHASE actually do?
<agg>
Sorry, this was a couple years ago and I didn't leave good notes, I'll try and remember and let you know :p
<Peanut>
Sounds like I need to make space on my desk for the good old oscilloscope again :-)
<agg>
I'm fairly sure I had some kind of mental model of what it was doing at the time so maybe I can resurrect it
<agg>
Heh probably the only way to be sure
<Peanut>
I have a 30 MHz crystal, and want to make 125 MHz out of it (to clock the SERDES, and an RGMII port. At the same time). However, the SERDES doesn't like the 125 MHz I give it. I know that's a clock issue, because my SFP cage comes with a 125 MHz clock, which it does like fine.
<agg>
Are you hoping the phase shifting will help? I haven't used the serdes but have had a 24MHz to 125MHz pll for rgmii... but I suspect that's the easy part
<Peanut>
The phase shifting is for creating the DDR clocks for the RGMII. I am also looking to see how much I can tune the PLL parameters (loop gain and bandwidth) to see if I can make a 125 MHz clock that meets the requirements for the DCU (SERDES).
<Peanut>
For RGMII (at least, for this one), eth_tx_clk needs to trail the transitions in the data bytes by 90°.
<agg>
Ah yep, that seems feasible
<agg>
Does your phy support internally shifting? Mine has a strapping/mdio option to add 2ns to both clocks which dramatically simplifies the gateware side
<agg>
I think many do
<Peanut>
Yes, it does, but that would mean implementing MDIO as well.
<agg>
hehe yea perhaps easier to just do the clock :p I did write an mdio impl anyway but my phy had it as a resistor strapping option so didn't need to bother
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<Peanut>
Now if only I could find my scope probes...
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<Peanut>
First finding: with CLKOS_CPHASE = 32, you get a nice 90° offset in my current setup. At 64, the signals are 180° apart.
<Peanut>
That was with CLKOP_DIV = CLKOS_DIV = 128. If I double the output frequency, I need a smaller shift, now 16 already suffices.