ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<whitequark> tnt: having seen code by chipmunks i have to disagree :D
<whitequark> care little enough and not even an US+ will save you...
<tnt> whitequark: Ah, I guess you have seen "better" chipmunks and I'll have to defer to your expertise in the matter then :D
<mewt> experience of those chipmunks sounds disquieting
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<RowanG[m]> I have a top entity that is generic because I want to use it on multiple board revision that are all the same save for a different ram chip that has differing number of banks.
<RowanG[m]> So I have a parameter on the top level module that specifies how wide the banks are
<RowanG[m]> I can read the verilog fine from yosys but I'd like to set this parameter before doing anything else
<RowanG[m]> But I can't seem to do it.
<RowanG[m]> So I call yosys with the verilog file.
<RowanG[m]> and do `setparam -set BANK_WIDTH 10 $abstract\Wrapper`
<RowanG[m]> which doesn't complain
<RowanG[m]> but when I then continue the default size of the parameter hasn't changed
<RowanG[m]> is there some other way I can do this?
<RowanG[m]> I tried to do it with defines but this doesn't work for some reason
<RowanG[m]> This fails with: `./wrapper.v:17: ERROR: Failed to detect width for parameter \BANK_WIDTH!`
<RowanG[m]> ooof this works I just missed the backtick...
<gatecat> RowanG: try doing `hierarchy -top Wrapper -chparam BANK_WIDTH 10` after reading verilog but before doing anything else
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<RowanG[m]> @gatecat thx :)
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