ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<tnt> What was the name of the plugin that was supposed to add full systemverilog support to yosys ? (not the paid one, the oss one)
<gatecat> tnt: uhdm and surelog?
<tnt> gatecat: Ah yeah, thanks !
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<stephe> What’s a good dev board
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<gatecat> stephe: what are you planning on using it for?
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<stephe> gatecat: just learning
<tpb> Title: 1BitSquared - iCEBreaker FPGA (at 1bitsquared.com)
<mewt> fabric speed is the main basic issue you'd run into with UP5k, I guess?
<tnt> IMHO while learning it's a good thing. You can code like a chipmunk and get stuff to fit and meet timing on a USP ... small and slow forces you to do things properly and build good habits.
<mewt> Certainly can't disagree, just wanted to give explicit warning :D
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