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tnt >
What was the name of the plugin that was supposed to add full systemverilog support to yosys ? (not the paid one, the oss one)
07:02
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gatecat >
tnt: uhdm and surelog?
07:03
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tnt >
gatecat: Ah yeah, thanks !
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stephe >
What’s a good dev board
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gatecat >
stephe: what are you planning on using it for?
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stephe >
gatecat: just learning
19:02
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tpb >
Title: 1BitSquared - iCEBreaker FPGA (at 1bitsquared.com)
19:04
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mewt >
fabric speed is the main basic issue you'd run into with UP5k, I guess?
19:05
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tnt >
IMHO while learning it's a good thing. You can code like a chipmunk and get stuff to fit and meet timing on a USP ... small and slow forces you to do things properly and build good habits.
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mewt >
Certainly can't disagree, just wanted to give explicit warning :D
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