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<flx>
I'm playing with u-boot on a Pine64 Quart64 board and discovered that u-boot has the shell command rockusb, an open implementation of the closed Rockchip USB protocol.
<flx>
Now I'm wondering if there are any alternatives using an open protocol. I like the idea of sideloading kernel images and such, reading from and writing to memory. fastboot maybe?
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<marex>
flx: DFU or UMS
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<flx>
marex: thanks. didn't think of dfu. interesting idea. i will look at that.
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<marex>
flx: DFU is USB-IF standard in fact , also look at dfu-ram (for upload of stuff into ram) and dfu-util (host system tool)
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<calebccff>
flx: fastboot is also super easy to use, but the "fastboot boot" command in normal android tools will pack whatever you give it into an Android boot image if it isn't already
<xypron>
marex: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name") which has been merged into origin/next breaks booting starfive_visionfive2_defconfig in the SPL stage. When on origin/master I enable the DEBUG_UART I see messages in SPL like: failed to get pll0_out device (parent of perh_root)
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<Tartarus>
calebccff: Go ahead
<marex>
xypron: ugh ...
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<xypron>
marex: In the device tree pll0_out is only listed in clock-names = of one of the clock controllers. Nowhere else.
<marex>
xypron: I think I know what it is ...
<marex>
xypron: are all of the clocks listed by phandle in clock-controller@13020000 { clocks = ... }; accessible in SPL ?
<marex>
xypron: i.e. do they all have bootph-* ?
<marex>
xypron: if not, the clock framework tends to bail on the inaccessible ones ... sigh ...
<calebccff>
damn what's Mateusz' nick again? have the same question about SPMI patches (if they can go through qcom)
<xypron>
marex: could you please build the defconfig locally. Then you can see this.
<marex>
xypron: I dont have a board to test , but I suspect that is what it is
<xypron>
But you only wanted to look at the device-tree?
<marex>
c02cdd41877b ("arm64: dts: imx8mn: Include 32kHz oscillator clock in SPL DTs")
<marex>
look at that ^ patch
<marex>
I ran into that issue before
<marex>
back in a bit
<xypron>
marex: the device-trees all come from Linux. So it would take quite a while to get any changes in
<xypron>
marex: drivers/clk/starfive/clk-jh7110.c seems to be where pll0_out is defined. Not in the device-tree.