<d1b2>
<fpga_zealot> Does ngscopeclient have a method for adding GPU (Vulcan) or FPGA Accelerators as filters?
<d1b2>
<azonenberg> All of the waveforms are stored in vulkan memory objects and we already accelerate a bunch of the filters like FFT and de-embedding
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<azonenberg> As far as FPGA acceleration we're not opposed to adding it but havent found anything it would be a good use case for
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<fpga_zealot> Yea, it would be rather difficult, you would probably want partial reconfiguration. You would need to support a good size library of static and partial bitstreams for each potential FPGA used.
<d1b2>
<fpga_zealot> I guess you could try to blackbox it and put it on the user. You just create a input and output for the FPGA and user has to use a template interface to process the data.
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<azonenberg> Anyway for now theres plenty of room to improve things with GPU acceleration
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<fpga_zealot> but I so many extra FPGAs laying around, but no GPUs... hehe
<d1b2>
<fpga_zealot> yea, GPU is probably a better common ground for everyone as well.
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<azonenberg> The other thing to consider is that gpus have built in FPUs and a ton of fast memory
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<azonenberg> unless you have one of the fancy virtexes with hbm2 you're unlikely to match that bandwidth
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<fpga_zealot> I have this
<d1b2>
<azonenberg> and typical scope waveforms are way too big to fit in block ram
<d1b2>
<azonenberg> yeah well i dont :p
<d1b2>
<azonenberg> cries in a corner looking at the recycled xcku5p he's reballing
<d1b2>
<fpga_zealot> yea, they are annoying to find and expensive, plus you need a paid license to develope it
<d1b2>
<azonenberg> exactly. while gpus are commodity
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<fpga_zealot> I waiting for another crypto crash to grab a few more
<d1b2>
<azonenberg> i'm not opposed to supporting e.g. alveo cards if i find a filter where it really makes sense and it outperforms a GPU
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<azonenberg> but so far gpu is the way to go and a lot of stuff is hard to even do that way
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<azonenberg> in particular we havent figured out how to parallelize CDR
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<azonenberg> i have ideas on how to get probably-good-enough CDR on a couple of threads by just chunking it up and doing a bit of postprocessing
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<azonenberg> it wont be enough for signoff grade eye patterns but might run a fair bit faster
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<fpga_zealot> I mostly a FPGA data flow guy, I need to start learning more about these filters.
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<fpga_zealot> I also got one of the new small Versal FPGA with those Processor Arrays (AIEs) kinda like a GPU where you can control the flow of data between processing nodes.
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<azonenberg> versals are not really fpgas they're a successor to zynq afaik
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<azonenberg> in that they have an arm soc and a bunch of other stuff too
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<azonenberg> I hope xilinx/amd keeps making pure FPGAs
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<azonenberg> without all the other bells and whistles
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<fpga_zealot> me too
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<fpga_zealot> I haven't heard anything new besides teh Sparten US+ they teased a few months ago
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<azonenberg> well what concerns me more is that versal is already on 7nm and there hasnt been a virtex or anything else since 16nm
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<fpga_zealot> most of the news I get are just flavors of the versal that are for bigger applications
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<fpga_zealot> They made something on the 5nm but locked it down just for AV1 encoding
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<azonenberg> exactly. they're all in on acceleration and "AI" and all that
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<azonenberg> and seem to be forgetting the asic prototyping and such applications :p
<d1b2>
<fpga_zealot> I keep you posted if any news leaks my way. I know my work would still ask for pure FPGAs, they buy the Versal and really only use the FPGA fabric, kinda sad.
<d1b2>
<azonenberg> yeah exactly
<d1b2>
<azonenberg> and i hate embedded linux and the whole zynq security model (i.e. PS as root of trust)
<d1b2>
<azonenberg> i'd much prefer the PL as root of trust
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<azonenberg> but for that to work it means the PS (if it exists) shouldn't be able to reconfigure the PL without its consent
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<azonenberg> or it can just deploy a new root of trust whenever it wants :p
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<fpga_zealot> Did you see that new linux patch suggested by AMD?
<d1b2>
<azonenberg> Yeah i didnt study it in detail but i saw it exists
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<azonenberg> they're seeing FPGA as an accelerator to the linux OS
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<azonenberg> while the systems i design are fpga dataflow centric and have a little cortex-m hanging off the side as a "state machine accelerator"
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<azonenberg> doing complex control plane protocol parsing that would otherwise need a giant rtl state machine
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<fpga_zealot> We may need to move Lattice Avant for this, I assume they will have a product in a few years that is Virtex-like and 7nm.
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<azonenberg> I'm eyeing efinix as well
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<azonenberg> their new gen parts are allegedly going to have 16 Gbps SERDES on them
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<azonenberg> and will be kintex class capacity
<d1b2>
<fpga_zealot> yea, I got the Ti180 eval kit, the tools are painful but thats nothing new
<d1b2>
<azonenberg> anyway, for now i'm a ways from outgrowing the free vivado compatible ultrascale/ultrascale+ parts
<d1b2>
<azonenberg> my biggest design to date is on the edge of fitting in a 7k160t
<d1b2>
<azonenberg> but it looked to be uncomfortably tight so i plan to put it in an au25p instead
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<azonenberg> (the scaled down prototype fit comfortably in a 7k160 but i dont know if i can fit the full size)
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<fpga_zealot> I wonder if the different CLB structure will help with your utilization in AU25P
<d1b2>
<azonenberg> Too soon to know
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<fpga_zealot> The AU25P does 16 Gbps really nicely
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<azonenberg> I'll be doing 2 lanes of 10.3125 10Gbase-SR and nine of QSGMII, tentatively
<d1b2>
<azonenberg> with one GTY unused
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<fpga_zealot> Do you have a repo for the code?
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<azonenberg> Here's the scaled-down prototype before adding heatsinks
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<azonenberg> 1000baseT management, rs232, 10G SFP+ on one side then 14x 1000baseT on the other using two different phy chipsets I was evaluating (TI DP83867, single port SGMII, and Microchip/Microsemi/Vitesse VSC8512, 12 port QSGMII)
<d1b2>
<azonenberg> fully open source layer 2 ethernet switch