sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<ornxka> i wrote -1 to mtimecmp but it didnt clear my interrupt
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<ornxka> it clears when i write 0xFFFFFFFF to it.. is the problem that it has to write to the register multiple times in order to write the whole 64 bits to it, and that its triggering a new interrupt in the middle of that due to having an intermediate value less than mtime?
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<ornxka> >For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are atomic.
<ornxka> guess not
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<ornxka> disabling interrupts, setting mtimecmp to -1, and then enabling them again also triggers a timer interrupt..
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<sorear> mtimecmp might be treated as signed on your platform, try writing 0x7F....FF to it
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