sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<ssb> is anyone working on riscv64-ilp32 ?
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<sorear> I've spent time agitating for people to keep __riscv_xlen and __SIZEOF_POINTER__ separate but I have not done explicit work on a port that would use that and I am not aware of other work in that area
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<pabs3> ssb: what would be the motivation for that? IIRC x32 (x86 equivalent) and the ARM equivalent were both abandoned
<ssb> pabs3, 10% performance improvement on pointer heavy workload (e.g compilation)
<ssb> x32 is not abandoned, it works, and it is being improved. It is just unusable on desktop due lack of support from web browsers/rust and such
<sorear> proper support for sstatus.UXL in cores and kernels would give you most of the same benefits with less effects on random software, but that requires buyin from hardware people
<sorear> there are some (niche within a niche) cases where you benefit from having 64 bit registers in a process limited to 32 bit addresses
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* pabs3 thought compilers often use more virtual memory space than 32-bit pointers allow these days, making non-64-bit ports less viable
<ssb> linux kernel compilation still comfortably fits in under 512 MB
<ssb> (unlike compilation of gcc itself, needs at leas 1 GB per core these days)
<ssb> and yes, few more years and that argument will be moot..
<cousteau> I recently compiled gcc and the gnu toolchain for RISC-V on a virtual machine at work
<ssb> still, 10% performance improvement is no joke
<cousteau> it ran out of memory
<cousteau> like, "trigger OOM Killer" kind of out of memory
<cousteau> so yeah, kinda RAM-intensive
<pabs3> I know Debian has hit virtual memory limits (not RAM limits) in some ports for some packages (maybe C++ with lots of templates), maybe that was only on MIPS, not sure
<sorear> with some care you can support 4GB of memory per-process in ilp32 (this requires making the (-2GB) to 0 region user address space, which could be controversial in the kerel)
<sorear> you will definitely have _some_ packages you have difficulty compiling, which makes this less attractive for distros that rely on a natively built gcc
<pabs3> hmm, I guess you could use a 64-bit compiler to cross-build those packages to ilp32
<cousteau> ssb: the way I see it, a 10% performance improvement means a jump of about 3 months, assuming performance scales with Moore's law (it probably doesn't)
<pabs3> Debian doesn't have cross-built ports yet though, although there are folks talking about various non-standardly built ports
<cousteau> sorear: heh, I've thought of negative memory addresses before. Sort of makes sense for 64b address spaces.
<ssb> cousteau, I agree with that. Note that it also applies to the usage of high level languages (C vs assembly), using optimizing compilers, profile driven optimization, link time optimizations -- yet people use that, universally.
<cousteau> alternatively, put the memory in 0xFFFF_FFFF_8000_0000..0xFFFF_FFFF_FFFF_FFFF rather than 0x0000_0000_8000_0000..0x0000_0000_FFFF_FFFF
<cousteau> What's the status of the Zbk* extensions for crypto? I recall reading about them somewhere, but I just checked the document for bitmanip v1.0.0 and there's no mention of any Zbk extension there
<cousteau> all I was able to find was a bunch of .adoc files in github
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<sorear> cousteau: not sure what you're getting at. ilp32 needs to use 'lw' not 'lwu' for loading pointers in order to not compromise compression, which means that they get sign extended
<cousteau> I actually can't remember how I reached that conclusion, but I think it had to do with being able to access any address with just two instructions (LUI + LD)
<cousteau> or if you want memory to be "contiguous", it can also be beneficial to have it laid out from 0xFFFF_FFFF_8000_0000 to 0x0000_0000_7FFF_FFFF
<cousteau> (it won't really be contiguous if you use unsigned pointers, but arithmetic will work as if it were)
<sorear> "being able to access any address" only helps you if you're doing position-dependent code
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<jrtc27> sorear: CHERI-RISC-V iss the mot real thing with __SIZEOF_POINTER__ != __riscv_xlen :P
<jrtc27> *is *most... somehow an s went walkie
<jrtc27> *
<jrtc27> *s
<jrtc27> grrr
<jrtc27> s hates me today
<jrtc27> but yeah, ilp32 flopped on amd64 where it had the most potential for being useful due to i386 register pressure
<jrtc27> ilp32 on arm64 (benefits from more registers again) is also basically non-existent unless you're dealing with apple watches
<jrtc27> for rv64 you don't even get that advantage
<sorear> at least A32 can do PIC
<jrtc27> there are indeed upsides of exposing pc a a general purpose register
<jrtc27> *as
* jrtc27 is beginning to think this keyboard is breaking
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