<zid>
I definitely didn't write it in a decent way but meh
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<geist>
hey no pasting of solutions!
<geist>
put spoiler tags
<geist>
(actually my fault for using a client that inlines those links)
<klys>
hurry hurry :)
<zid>
3 minutes left geist :p
<zid>
less than 2!
<klange>
Not like there's some limit on when you can submit...
<kazinsal>
someone I know has been doing advent of code in awk and by day 4 they were regretting it
<zid>
meh I might as well start on day 10 I suppose..
<moon-child>
kazinsal: heh, same
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<klange>
137... that's my best second part placement so far >_>
<eryjus>
no competition here i see
<klange>
I got 101 on the first part of day 8, so you can imagine my annoyance.
<zid>
hang on I am still reading :p
<moon-child>
I got some place in the low hundreds on I think day 2
<moon-child>
kinda lost interest and haven't done any problems since
<klange>
Most of the folks who stick with it have some additional challenge they've made for themselves, like doing it in a new language or a particular unsuitable one.
<zid>
Mine segfaults I win
<zid>
best I ever got was 36th
<zid>
not bad for C :p
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<gorgonic->
I was doing mine in ocaml and after I spent like four hours writing support code because I refused to use the batteries included library I lost interest also
gorgonic- is now known as gorgonical
<gorgonical>
why was my name mangled? anyway
<kazinsal>
IRC works in mysterious ways
<gorgonical>
ocaml is fun but I don't know it very well and I have arguably more productive things to be doing than spending 4+ hours on increasingly difficult problems. I was enjoying it for around 2 hours per problem
<zid>
Just do them in 4 minutes smh
<gorgonical>
I seriously felt that when I was doing the bingo board one. Like... this would be trivial to do in memory with ptrs, but instead I was modeling the whole bingo board like a dingus because I didn't know how else to do it in ocaml
<zid>
I'm completely baffled by this code bug, whatever it is
<zid>
I'm completely baffled by this code bug, whatever it is
<zid>
You are not my terminal
<Mutabah>
/home/zid$
<zid>
It's seemingly getting inside an if that I am printfing the value for the test which it does not match
<gorgonical>
Could it be coherence?
<zid>
if(blah) return 1197; printf("made it\n");
<zid>
Made it
<zid>
line 3, score 1197
<geist>
wat.
<geist>
well what's after the printf?
<zid>
It mirrors the value in that exact statement too
<zid>
oh shit
<zid>
thanks geist
* zid
adds 'return 0;'
<geist>
riiiight was just asbout to say if you had no return then it returned what was ever in rax/x0/etc
<geist>
and it's possible i had pre-loaded it with 1197 because
<zid>
How does that end up in rax I wonder
<zid>
it obviously DOES
<geist>
depends on the codegen really
<zid>
but I wonder how.. maybe I will copy the binary
<gorgonical>
compiler shenanigans
<geist>
having no return shold be a big fat warning though that you shouldn't ignore
<geist>
but since that is UB, the compiler can do what it wants
<Mutabah>
Annoyingly, it's not on by default in far too many compilers
<zid>
I have -W but got no warning :/
<gorgonical>
I have learned -
<zid>
or I printf spammed too much and missed it idk
<gorgonical>
Wall -Wextra is my friend
<zid>
I don't like wall wextra while golfing though
<gorgonical>
Really I just wish c was ada actually
<geist>
so the code could have been something like 'load rax, 1179; cmp blah; beq no_return; ret; no_return: printf; ret;
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<geist>
or... actually probably
<zid>
there are 4 of those exact ifs and 1197 is the 2nd of the 4, geist
<geist>
sinceit's common for the compiler to branch to a common exit path like that with the return value already preloaded in a register
<zid>
anyway, it worked after that
<geist>
reminds me, i found a fun new undefined compiler behavior at work the other day
<geist>
had a function that had an infinite loop. basically a panic 'kill the kernel right here and dont continue' function
<geist>
looked something like die() { disable_ints; for(;;); }
<geist>
guess what clang decided to do with that?
<Mutabah>
Remove it entirely
<geist>
close!
<Mutabah>
Probably made the entire function `UD2`?
<klange>
disable ints _after_ the loop?
<Mutabah>
No loop?
<geist>
any more bets?
<klange>
no loop would have been my next
<geist>
simon says: no loop, and just falls off the end of the function
<geist>
so doubleplus bad
<geist>
die: call disable_ints; ....
<Mutabah>
Infinite loops are UB yo
<klange>
not anymore
<geist>
yep. it was an oversight *anyway*, should at the minimum stick a WFI or yield or something in there to just not burn power
<klange>
c11 says if the loop expression is a constant you're fine; the older specs were based solely on the contents of the loop - loop does nothing? no loop!
<geist>
ayway the compiler deciding to just fall off the end of the function is a real jewel
<klange>
in a discussion about asserts over in a discord, someone posted a code sample that accidentally missed a return statement despite have a return type
<geist>
so protip: no more naked infinite loops. just say no!
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<geist>
at least put a asm("nop") in it
<klange>
like `int foo(int num) { if (!num) { some_fail_function(); } assert(num); }`
<geist>
huh and no warning on that?
<zid>
part 2's final step was weird, all done though
<klange>
and both gcc and clang eliminated the if and forced the call to some_fail_function and __assert_failed
<geist>
oh because some_fail_function() is no-return?
<klange>
presumably because __assert_failed is
<geist>
it's possibly because it's no return, so it figures both paths dont exit
<zid>
Looks like I did p2 in 6 minutes, overtaking 1400 people compared to part 1 which took me.. forever
<geist>
one i've also seen that's really annoying is something like
<klange>
no return → that's UB, but __assert_failed does not return so that path must be the only correct one therefore the if must always be true therefore here's two calls and no return :D
<zid>
I mean, it should not be possible for anyone to *compile* you sending dumb crap, but the C spec fucking sucks at enums
<klange>
(C++, though, not C)
<zid>
nobody should actually use C enums as types
<zid>
they don't work
<geist>
zid: yeah but they can roll some int and pass it in. but that's the real answer. C++ fixes it nicely with proper enum classes, which i think is where they get useful
<zid>
all the enum values are compatible with each other for very starters
<geist>
that's oen of those absolutely better things that C++ does
<zid>
yea there are so many braindead things in C that would be perfect with some minor alterations since *checks watch* 1989.
<zid>
Instead we got _Complex and stuff
<zid>
because they were handmedowns from the C++ committee
<geist>
yah C is like the little starving kid getting food from Scrooge
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<geist>
yes sir thank you sir
<kazinsal>
*staring down at a bowl of sigsegvs* please sir, may I have some more
<zid>
It's more like.. the crazy aunt keeps giving you christmas presents that are obviously used jumpers that are 8 sizes too big and say BLACK AND PROUD, despite you being a 9 year old white girl
<kazinsal>
thinking of building a new server with a 5800X
<zid>
5800x is nice
<zid>
That's the amd cpu I'd buy
<geist>
ryzen you mean?
<geist>
ah yesh
<kazinsal>
yeah
<kazinsal>
should handily kick the ass of my 2x E5 2650 machine
<geist>
so interesting: i think i may have pushed my 3950x a bit too far. it was my main desktop for 2 years, slightly overclocked
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<kazinsal>
while also booting in a tiny fraction of the time
<geist>
i got a 5950x to replace it and moved the 3950x into the server
<geist>
and... it has crashed twice now over the last few weeks
<geist>
hard lock up, no MCE. no reset. just hard stop
<kazinsal>
interesting
<zid>
I've still yet to kill a cpu
<kazinsal>
give it a bit more voltage at stock clocks imo
<zid>
My xeon's on a 50% OC
<zid>
It ran out of multiplier at that point
<kazinsal>
shouldn't need the full monty, just maybe 50-70 mV over stock
<zid>
it's also undervolted.
<geist>
yah possibly works
<zid>
Or it's just.. a faulty mosfet on the mobo
<zid>
who can tell
<geist>
but it does make an excellent VM host chip, aside from it being crashy
<zid>
I have a fun graphics card which I am like 99% sure has a faulty VRM
<zid>
It works 100% flawlessly, until it enters turbo, then crashes reliably
<zid>
So it's 100% stable if you.. disable the turbo, then overclock the shit out of the non-turbo performance state to be >= the turbo state
<zid>
I think it enables extra power rails when it goes into turbo state, and one of them is broken
<zid>
and they aren't needed except for very extreme overclocking
<geist>
another nice advantage of consumer ryzen servers: ECC actually works
<geist>
though you dont get very solid ECC reports
<kazinsal>
yeah, no need to buy a big fancy epyc board
<kazinsal>
just grab a board and a CPU and some unbuffered ECC DDR4
<geist>
watching this guy dig a tunnel under his house
<geist>
he's a pretty crazy guy
<gorgonical>
furze is wild
<zid>
colin furze :P
<geist>
yep
<gorgonical>
i've been wondering how he got permits for this
<zid>
his accent is super similar to my home town, the one I refuse to use
<geist>
exactly
<kazinsal>
I was gonna say "oh, season 1 of Bosch" but that's because I'm binge rewatching it ;)
<gorgonical>
I've been hemming and hawing about building a shed sauna and this guy is digging a mine tunnel in his backyard
<bslsk05>
'1947 Electronics - Will It Still Work Today? Find Out!' by Mr Carlson's Lab (00:17:58)
<geist>
good to just have going in the background when doing stuff
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<gorgonical>
Holy moly that radio still works
<gorgonical>
Also that electronics work in the bottom is positively horrifying
<geist>
ahaha you actually watched it
<geist>
yeah it's kinda fun watching him go through old stuff, and it's so Canadian
<gorgonical>
It makes me wonder how much you could change history by introducing the breadboard or even the PCB back then
<gorgonical>
Instead of having to wire every component directly in rat's nest fashion
<geist>
yeah
<geist>
i've seen lots of this sort of electronics, my dad is always working on old tube type ham radios
<geist>
if you dig around he has a few 'look around my lab' videos, and he has a ridiculous amount of equipment
<gorgonical>
that intro really shows it too. Insane
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<kernelspace>
Bitweasil: thanks, is SCR.NS always readable from sec/nonsec ?
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<geist>
kernelspace: the secure/insecure bit on ARM?
<geist>
from quickly grepping around the ARM v8 ARM it would appear there's nothing obviously that masks it
<gorgonical>
kernelspace: to echo what geist said, I checked the manual. According to D13-3395 there's no clear mask on a specific bit. Looks like the only access requirement is EL3
<geist>
in armv8 it looks like SCR_EL3.NS is where it exists, and thus is only readable from EL3
<geist>
so i guess that maps directly to arm32s SCR
<geist>
but it being in EL3 only means most applications/oses/hypervisors cannot read it
<gorgonical>
yeah, that's like optee territory
<gorgonical>
opt-tee?
<gorgonical>
op-tee, apparently]
<geist>
yeah
<geist>
i am refreshing my memory on precisely how it switches the .NS bit on exception entry/exit into EL3
<geist>
is it saved as part of SPSR? since there's only one .NS bit maybe it only applies to <=EL2?
<gorgonical>
I don't have much experience with in/secure states. I know there's some pretty complex routing for exceptions, but I don't know if that's architectural or expected to be enforced by the EL3 firmware
<geist>
oh yeah that's what it does
<geist>
SCR.NS only affects the lower levels
<geist>
EL3 is always intrinsically in secure mode
<gorgonical>
I see
<gorgonical>
So the exception routing model is just a suggestion for compliant el3 firmware
<gorgonical>
"suggestion" maybe is a better phrasing
<geist>
0b0 Indicates that EL0 and EL1 are in Secure state.
<geist>
0b1 Indicates that Exception levels lower than EL3 are in Non-secure state, so memory accesses from those Exception levels cannot access Secure memory.
<geist>
well, i think it's pretty much wired up to work a particular way
<zid>
0b0e indicates woodwind mode (sorry!)
<j`ey>
zid: :D
<geist>
it also mentions elsewhere that if an implementation does not implement EL3 it's IMPLEMENTATION DEFINED what security mode the cpu operates under
<geist>
(since it still has to set the security bits on AXI bus transactions, etc)
<geist>
for some reason i was always thinking the .NS bit was mirrored all the way down, but nope
<geist>
but there's a newer feature that gives secure EL2 in which case it also i think mirrors it down one more level
<geist>
FEAT_SEL2
<gorgonical>
I'm not really understanding D1-2316 (d.1.4.1) here
<geist>
ah SCR_EL3.EEL2 is a new bit that controls secure EL2 if FEAT_SEL2 exists
<gorgonical>
It says security state can only be changed by taking exception to el3.
<geist>
right, or back
<gorgonical>
This is that NS bit? I mean, or is this just "you're in EL3 now and that's secure"?
<geist>
ie you can go from lower security to higher on an exception to EL3, and back
<gorgonical>
It must be the latter, right?
<geist>
it says that EL3 is *always* secure
<geist>
so the SCR.NS bit controls the levels below
<geist>
whether or not when you switch to EL2 or EL1 or EL0 it'll turn the secure bit back off
<gorgonical>
Oh I see
<geist>
so the state isn't saved anywhere on exception entry, it's part of an EL3 control register
<gorgonical>
But you can have secure EL2/1/0 right? So if it's toggling NS off then how can EL3 control it?
<geist>
sure in that case you simply leave SCR_EL3.NS = 0
<geist>
EL3 can set it whenever it wants, it just has to be in EL3 to do it
<geist>
so if you're bouncing between secure and insecure EL1s for example, you have to do it via an exception to EL3, which can then fiddle with the bit
<geist>
it's part of the state the EL3 monitor would save and restore as it switches contexts
<gorgonical>
Right, so this is just intel SDM-style "here is exactly what you cannot do" and you have to read in between the lines
<gorgonical>
That's what my understanding of the situation was, that el3 just has to moderate the switches from in/secure states
<geist>
yah, the EL2 virtualization stuff is very much that way in ARM since it's basically a bunch of tools you can build a hypervisor out of
<geist>
and in general yeah, EL3 primarily exists to have a higher authority than anything else to switch secure contexts
<Belxjander>
3 layers of exceptions ???
<gorgonical>
I was just thinking that it's arbitrary that we stop at el3. Like you could have a metasecure layer and tack on el4.
<gorgonical>
4 actually, there's an el0
<gorgonical>
Obviously I don't know what use a metasecure layer is lol
<geist>
and as we've mentioned before, apple apparently didn't decide they needed secure mode so they simply left out EL3
<gorgonical>
But don't they have codesigning and tpms and stuff? That's just part of the el2 stuff?
<geist>
i think their strategy is to rely more on external (or internal to the die) secondary processors
<geist>
vs needing some sort of secure mode OS
<gorgonical>
I see
<Belxjander>
j`ey: yikes... and here I was thinking about whether to try getting something Android ARM based working on something else in a wrapper HLE layer setup... **way** too much work for the time I do have ...
<geist>
makes sense if you build your own hardware: add more dedicated processors to do that stuff
<gorgonical>
Belxjander: I am exaggerating a little since you can't take exceptions to el0. Though you do have an el0 timer
<geist>
Belxjander: it's not too bad. actually i think it makes a nice logical sense since for the most part they nest in a fairly intuitive way
<gorgonical>
Honestly one of my favorite features of ARM so far has been the system-wide counter. Holy moly does it make benchmarking virtualization and core-migrating easier
<geist>
yah right?
<gorgonical>
Here I am mincing again about whether SIPI sequence on x86 refreshes core tsc or not since I am doing virtualization reconfiguration on x86
<geist>
FWIW riscv is also following more or less the same model: machine mode == EL3, supervisor mode = EL1, user mode EL0
<geist>
and their new hypervisor extensions are kidna a pseudo EL2, though not precisely
<gorgonical>
tbh the VHE part of arm confuses and disappoints me. I was hoping to be free of "but if you enable *this* bit then all this shit works differently from normal because compatibility"
<geist>
yah, sadly i think the VHE part is kinda like admitting the intel model isn't half bad
<j`ey>
Belxjander not sure what a HLE wrapper is..
<gorgonical>
don't say it. I don't want it to be true
<geist>
my initial thought a long time ago when i realized everything is just going page tables now and all the other styles of MMUs are dying out
<gorgonical>
I have only limited experience with other MMUs. Once I read a paper from... Xerox? About a grid-memory MMU
<geist>
and everything is little endian, etc etc. the effect that x86 has had on everything is profound
<gorgonical>
That was wild
<gorgonical>
part of the paper was "yeah we just fabbed this chip out to prove it would be useful" as though it were so casual. Hilarious
<geist>
heh yeah
<j`ey>
gorgonical: VHE just means linux didnt need a rewrite :P
<gorgonical>
j`ey: cowards! the lot of them
<geist>
if you consider the sum of all architectures that have ever existed, really all the modern remaining things are far closer in design than they are apart
<gorgonical>
geist do you have some pointers for mmus that aren't page table centric? I have so little experience it hadn't even occurred to me you'd use something else
<geist>
power/ppc uses a large single hash table, which is pretty trippy
<geist>
ia64 had *two* kinds of page tables, one of which is a large virtual page table, very trippy
<gorgonical>
power had to have it to go along with their crazy tlb where you can put whatever you want in any way in it, I guess
<geist>
and lots of mid 80s or lower end risc machines had TLB miss exception based hardware: software provides the data structure
<gorgonical>
whoa
<gorgonical>
Yeah sure why not? Get a tlb miss exception and just deal with it
<geist>
ultrasparc is a good example, or say SH or microblaze or nios 2 or whatnot
<geist>
lots of lower end risc machines
<geist>
yep. also lower end embedded ppc machines have a TLB miss mode i believe
<geist>
ia64 has a tlb miss mode too, though it serves the virtual page table thing, which i think i understood at one point in my life and then forgot
<gorgonical>
part of me is sad that I wasn't old enough to play with all these architectures. I sometimes feel like I got on this train late and everybody's doing a different thing now, what with the CPU trending toward an accelerator manager
<geist>
yah its one of the reasons i like to keep some of them alive a bit. i graduated college right as everything collapsed. ia64 killed everything all at once
<j`ey>
gorgonical: same
<geist>
it was going to be the Next Big Thing and everything died at once
<gorgonical>
honestly being in HPC research is a little sad. Like summit and sierra are basically just chips hosting a stack of GPUs now. I think fugaku is a little better but it's basically the same
<geist>
not that a bunch of unix companies producing their own workstations with their own architectures was going to survive any longer anyway
<geist>
ia64 was just the nail
<gorgonical>
"how fast can we get data into and out of the GPU blackboxes?"
<gorgonical>
and how much of our souls are we willing to sell to nvidia for it
<j`ey>
fugaku.. if the fujitsu one, is some custom arm CPUs that's cool gorgonical !
<gorgonical>
j`ey: yeah the fujitsu one. It is indeed extremely cool to deploy fast arm chips
<zid>
gorgonical: if you think the cpu is an accelerator manager now, try a 486 box
<gorgonical>
Other labs have the cavium thunder x2 chips, but fujitsu really took the ball and ran with it
<zid>
with a discrete sound card, discrete vga card, discrete network card, discrete pci bus, blah blah blah
<gorgonical>
zid: that is true. I have been lectured about the horrors of emulating PCI chips and how absolutely none of it makes sense
<gorgonical>
Basically reverse-engineered code with comments like // ???
<zid>
gorgonical: who doesn't like discrete L3 cache, also
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<gorgonical>
but then nvidia bought arm, too! and now the ship has several compartments breached
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<klange>
One of my USB hubs just crashed and did not reset when unplugged... because it was retaining power from an AC adapter.
<zid>
I hate haunted hw because power loss didn't cremate the ghost living in it
<zid>
had that happen a few times with motherboards, no amount of power cycling would fix them until I left it turn off for 5 minutes
<zid>
which led me up a bunch of garden paths trying to diagnose it
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<kernelspace>
geist: i am in arm v7, wondering if NS bit is readable always, from sec or non sec workld
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<clever>
kernelspace: i would assume it is, at least for kernel space, so you can even know which mode your in
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<kernelspace>
clever: thanks
<kernelspace>
and thansk all of this great helpful channel
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<geist>
kernelspace: i'm guessing no, unless you're in EL3
<geist>
though v7... maybe. but v8 seems to generally hide it, so i wouldn't be surprised if that's not consistent with v7
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<kernelspace>
geist: mm, well, i am in u-boot spl, from some asm code, trying to understand if i am in sec or ns
<geist>
ah
<kernelspace>
not very skilled on arm7 stuff, at this level. So, if i am understanding, EL3 is secure world, correct ?
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<kernelspace>
so doing
<kernelspace>
mrc p15, 0, r0, c1, c1, 0
<kernelspace>
bit 0 seem set to 1
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<kazinsal>
vacation approved, concert ticket acquired, gonna do a couple days in Seattle in March to unwind :toot:
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<zid>
kazinsal: something something sleepless hur hur
<kazinsal>
that depends on a few other things going well first hur hur hur
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<zid>
I didn't know you were into all-night games of D&D to that degree.
<kazinsal>
that's more like a consolation prize
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<sortie>
kazinsal, boom
<sortie>
Who you seeing?
<kazinsal>
Queensryche and Judas Priest
<sortie>
That's awesome
<gog>
nice
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<kazinsal>
and if I manage to muster up enough courage (which may involve this bottle of wine work sent me) I maaaaaay end up asking someone I hang out with regularly online and play a few video games with who lives in Seattle out for dinner
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<j`ey>
kazinsal: shoot ur shot
<sortie>
go go kazinsal
<zid>
kazinsal: I'm honored, which games?
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<klange>
I think that was 'aarch64' getting sentence-cased but okay
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<j`ey>
LGTM other than that
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<bauen1>
so long story short, is there a way to compile gcc with a "freestanding libstdc++-v3" without any libc for the target ?
<bauen1>
that must be something that people do right ? like if you're trying to use C++ in the kernel you won't have a libc, but you wants libstdc++-v3 for the cstdint headers etc... ?
<sortie>
klange, what! A release!
<sortie>
How dare you
<sortie>
Oh man what a beautiful wallpaper and about toaruos screenshot at the top!
<bauen1>
klange: you ported your kernel to 64 bit ?
<klange>
bauen1: no, I mostly wrote a new one
<klange>
and then copied over the bits that didn't need any 'porting'
<klange>
eg. vfs, and other high level things
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<sortie>
klange: “, a loopback,” ← Maybe be explicit and say loopback interface?
<klange>
ack, edited
<moon-child>
klange: 'A dynamic linker (ld.so)' doesn't end in a period, unlike all the other bullets
<klange>
ack, ty
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<moon-child>
'Kuroko first appeared in [...]. Kuroko has [...]' feels a bit repetitive and awkward. Maybe go for 'Kuroko first appeard in [...], but has improved greatly'
<moon-child>
(or maybe and instead of but, not sure which reads better)
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<zid>
Great improvements..
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<sortie>
klange, a bit too tired to give a proper thorough review but overall what an impressive release and the release notes really sells that
<klange>
sortie: Thank you :) The plan is to post everything tomorrow, so there is plenty of time to make sure the release notes are in good order.
<eryjus>
Klange, bring "release 2.0" into the opening paragraph (versus "this release")
<klange>
There will be a title "ToaruOS 2.0" on the actual release notes.
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<eryjus>
my thought process; i think it is important to have that fact stand on its own in the first paragraph. also iirc, everything is your own code (nothing ported)... is that correct?
<eryjus>
i have not gotten all the way through the notes yet, but it that called out?
<eryjus>
i think it's something to be proud of and celebrate
<klange>
It's in there a few times.
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<eryjus>
ha! i was going to ask when we would see an aarch64 port.
<eryjus>
nice, klange!
<eryjus>
ok, bullets in "Features of Misaka" have no periods; bullets in "Changes since 1.14.1" do
<eryjus>
Also recommend capitalizing "Since"
<eryjus>
If you add periods to "Change ....", "New userspace utilities exposing functionality added in Misaka: top, strace, dbg, ping, cpuwidget" has no period
<zid>
I recommend inverting it and changing it to Erstwhile
<klange>
zid: I don't think there's a logical way to do that.
<eryjus>
Consider rewording to "Many more things of which I lost track."
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<zid>
klange: I'm surprised you even bothered to respond to that :P It's technically doable though, 'Erstwhile versions lack the following features', I hate it :D
<eryjus>
ok, back to my own shitty kernel
<zid>
eryjus: is that the title of your next novel? I would read it
<zid>
Back to my own shitty kernel - Volume 01 [J-Novel Club][Kobo_LWNCentral].pdf
<bslsk05>
www.merriam-webster.com: Ending Sentences With Prepositions: Is it Allowed? | Merriam-Webster
<moon-child>
zid: the point of grammar rules is to promote communication
<moon-child>
so the question is: it is harder to understand sentences which end with prepositions?
<moon-child>
I don't think so (though obviously you can argue that)
<klange>
I very often find it harder to understand the twisted garbage someone produced trying to abide by "the rule".
<moon-child>
yes
<zid>
If you want to fix english just split 'put' into two forms thanks
<zid>
I mean I guess place technically exists.. maybe we just make that the rule! new rules yay!
<moon-child>
zid: if we re-place it with 'place', then where would 'put' be put?
<zid>
in the past tense where it belongs, or in the present opposing placed
<zid>
flip a coin
<zid>
sit/sat, eat/ate, put/put
<moon-child>
hmm
<moon-child>
so will you replace a golf 'putter' with a 'placer'> :)
<moon-child>
s/>//
<zid>
That has no tense so it's fine
<klange>
putt is a different word than put ;)
<zid>
also yea it's a putt-er
<zid>
technically
<moon-child>
right
<zid>
Also we teach americans about the sentence form "The man was stood still"
<zid>
apparently large amounts of americans can only read the word 'stood' to mean 'was placed'
<zid>
past participle? idk grammar
<zid>
Quote from a prescriptivist american blog I just googled
<zid>
"It is perfectly correct to say, “I was stood at the bus stop” — but only if someone picked you up physically, walked you to the bus stop, placed you down and stood you there."
<moon-child>
eh I don't buy that even under the prescriptivist ideology
<moon-child>
first: nothing to say you can't already have been at the bus stop when you were stood; second: nothing to say you can't have stood yourself
<zid>
Yea I think it probably comes from the latter
<zid>
just a unification between being forced to stand there and forced yourself to stand there
<klange>
how is that any different than 'was standing'
<zid>
hence: I stood
<kingoffrance>
that sounds like a horrible date that went horribly wrong
<zid>
It isn't, it's just how I talk
<moon-child>
kingoffrance: lol
<klange>
kingoffrance: that's being stood up!
<klange>
aaaand 'stood' is now semantically satiated in my mind, and I'm now reading it like stewed
<zid>
laid and sat also act the same way to me
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<kingoffrance>
If it wasn't for my horse, I wouldn't have spent that year in college </lewis black>
<eryjus>
zid: lay and lie. go.
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<zid>
hmm?
<zid>
Go where, go lay down? :p
<zid>
I think this might actually be active vs passive
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<zid>
"Where his remains lay" "where his remains were laid" "He was standing" "He was stood"